diff options
| author | Kenji Chen <kenji.chen@intel.com> | 2014-09-30 14:17:35 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-04 12:40:05 +0200 |
| commit | 94fea491df7beaf02b2cd01d3b4366e9baa82a89 (patch) | |
| tree | 79f910cb65fda4dc3dfb29a0ce3cfbaab135b757 /src/soc | |
| parent | e1ca8a3d42da15fbe7a8be928bdd531f26298dd6 (diff) | |
Broadwell: Fix PCIe L1 Sub-State capability ID not filled.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 31d7276fbdca67937bcdf0d5c2af371a2fd1a510
Original-BUG=chrome-os-partner:31424,chromeos-os-partner:32380
Original-TEST=Build a BIOS image and check the value is applied correctly.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: I0adda3643776b259a635a021babd983090f1df43
Original-Reviewed-on: https://chromium-review.googlesource.com/220475
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id88c11ed128b44c3a60ef1a141b99071c1ee15d3
Reviewed-on: http://review.coreboot.org/9267
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/pcie.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 4e5bbfa015..10b623098b 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -558,9 +558,12 @@ static void pch_pcie_early(struct device *dev) pcie_update_cfg8(dev, 0xf5, 0x0f, 0); - /* Set Extended Capability to offset 200h and Advanced Error Report. */ + /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); + /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ + pcie_update_cfg(dev, 0x200, ~0xffff, 0x001e); + pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6), (1 << 20) | (3 << 6)); /* Enable Relaxed Order from Root Port. */ |