diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2024-07-18 21:08:30 +0100 |
|---|---|---|
| committer | Sean Rhodes <sean@starlabs.systems> | 2024-10-11 08:31:52 +0000 |
| commit | 1d535eb467c3a9119ec3022494ded8b06bf7ab28 (patch) | |
| tree | 3671cd54be0daa7ad25658e3f9b34b3ca84eb842 /src/soc | |
| parent | 9394bace4e798197414bc8e05be0bcbc0a767fe7 (diff) | |
soc/intel/cnvi: Add _S0W to ensure CNVi isn't put into D3 Cold
All CNVi modules, integrated or dedicated only support D3 Hot
so add _S0W to limit the sleep state.
Intel document #559910 details this.
Change-Id: I1541cebc022adc927a9cd883500320e9ef82359f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/cnvi/cnvi.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 609c473341..afe08c5120 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -86,6 +86,18 @@ static void cnvw_fill_ssdt(const struct device *dev) acpigen_write_field("CWAR", fields2, ARRAY_SIZE(fields2), FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE); +/* + * Method (_S0W, 0, NotSerialized) // _S0W: S0 Device Wake State + * { + * Return (ACPI_DEVICE_SLEEP_D3_HOT) + * } + */ + acpigen_write_method("_S0W", 0); + { + acpigen_write_return_integer(ACPI_DEVICE_SLEEP_D3_HOT); + } + acpigen_pop_len(); + acpigen_write_scope_end(); } |