diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-03-11 16:40:20 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-15 19:17:12 +0000 |
| commit | 129b8ae5515017a7417fbb7c7d0ede482fd4d1a1 (patch) | |
| tree | fd8b69c4923700b8ea9efccd6f800de89b811eb3 /src/soc | |
| parent | a4cdb5b381c92079ad7dae68b02599f3e7cec063 (diff) | |
soc/mediatek/common: Add halt() after triggering wdt reset
It's more reasonable to halt when we trigger watchdog reset because
the whole system should be reset afterwards.
BUG=b:222217317
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/common/wdt.c | 32 |
1 files changed, 21 insertions, 11 deletions
diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 4f8eff282e..108648f80f 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -3,11 +3,31 @@ #include <arch/cache.h> #include <device/mmio.h> #include <console/console.h> +#include <halt.h> #include <soc/wdt.h> #include <vendorcode/google/chromeos/chromeos.h> __weak void mtk_wdt_clr_status(void) { /* do nothing */ } +static inline void mtk_wdt_swreset(void) +{ + /* + * We trigger a secondary reset by triggering WDT hardware to send the + * signal to EC. + * We do not use do_board_reset() to send the signal to EC which is + * controlled by software driver. + * Before triggering the secondary reset, clean the data cache so the + * logs in cbmem console (either in SRAM or DRAM) can be flushed. + */ + printk(BIOS_INFO, "%s() called!\n", __func__); + + dcache_clean_all(); + setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + + halt(); +} + int mtk_wdt_init(void) { uint32_t wdt_sta; @@ -23,17 +43,7 @@ int mtk_wdt_init(void) if (wdt_sta & MTK_WDT_STA_HW_RST) { printk(BIOS_INFO, "hardware watchdog\n"); mark_watchdog_tombstone(); - - /* - * We trigger secondary reset by triggering WDT hardware to send signal to EC. - * We do not use do_board_reset() to send signal to EC - * which is controlled by software driver. - * Before triggering secondary reset, clean the data cache so the logs in cbmem - * console (either in SRAM or DRAM) can be flushed. - */ - dcache_clean_all(); - setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); - write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + mtk_wdt_swreset(); } else if (wdt_sta & MTK_WDT_STA_SW_RST) printk(BIOS_INFO, "normal software reboot\n"); else if (wdt_sta & MTK_WDT_STA_SPM_RST) |