summaryrefslogtreecommitdiff
path: root/src/soc/ucb/riscv
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2020-11-18 12:27:28 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-11-22 22:26:25 +0000
commit02dec12629824174e788658f40b79bdd5337ffa7 (patch)
treeec030bed8bdf56ee589c350c82267d41075bcac6 /src/soc/ucb/riscv
parent832dd4388a8f8a56acd70da5c1cdfa97deb3bf5d (diff)
soc/intel/xeon_sp: Work around FSP-T not respecting its own API
The CPX FSP-T does not respect the FSP2.x spec and uses registers where coreboot has its initial timestamp stored. If the initial timestamp is later than some other timestamps this messes up the timestamps 'cbmem -t' reports as it thinks they are a result from a timestamp overflow (reporting that it took 100k years to boot). TEST: The ocp/deltalake boots within the span of a lifetime. Change-Id: I4ba15decec22cd473e63149ec399d82c5e3fd214 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions