diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2020-03-30 20:15:01 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-04-21 05:48:21 +0000 |
| commit | ef5ff0b49a5d61b8dfc313fdddba3f07e3f7a8fc (patch) | |
| tree | 850d9d0f79ed4bf2834adbd1a5db6bb9021e4dc2 /src/soc/ucb/riscv | |
| parent | aa832c19b2c3e4f1be6b917abd962a7d664be7a3 (diff) | |
mb/intel/jasperlake_rvp: Enable Wifi and BT
Enable Wifi and Bluetooth for Jasper Lake RVP with following changes:
1. Enable related pci root ports for WLAN and BT
2. Disable unused root ports and clkreq for unused clocks
3. Configure GPIOs properly for M.2 port
BUG=None
BRANCH=None
TEST=Code compiles and able to detect Wifi/BT module on board.
Change-Id: Ifbd07022c05769c04ecd49c81a4430947125b32a
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39933
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions