soc/sifive/fu740: Add FU740 SOC

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>

6 files changed, 165 insertions, 0 deletions

diff --git a/src/soc/sifive/fu740/include/soc/addressmap.h b/src/soc/sifive/fu740/include/soc/addressmap.h
new file mode 100644
index 0000000000..e2aa7314f6
--- /dev/null
+++ b/src/soc/sifive/fu740/include/soc/addressmap.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// reference: fu740-c000 manual chapter 5: Memory Map
+// Table 15: (TODO: subject for common code: none of these changed compared to fu540)
+#define FU740_ROM        0x00001000
+#define FU740_DTIM       0x01000000
+#define FU740_CLINT      0x02000000
+#define FU740_L2LIM      0x08000000
+#define FU740_PRCI       0x10000000
+#define FU740_UART0      0x10010000
+#define FU740_UART1      0x10011000
+#define FU740_QSPI0      0x10040000
+#define FU740_QSPI1      0x10041000
+#define FU740_QSPI2      0x10050000 // in unmatched board schematics it's called SPI0
+#define FU740_GPIO       0x10060000
+#define FU740_OTP        0x10070000
+#define FU740_PINCTRL    0x10080000
+#define FU740_QSPI0FLASH 0x20000000
+#define FU740_QSPI1FLASH 0x30000000
+#define FU740_DRAM       0x80000000
+
+#define PCIE_MGMT   0x100D0000
+#define PCIE_CONFIG 0x000DF0000000
+#define PCIE_DBI    0x000E00000000
+
+#define FU740_I2C_0 0x10030000
+#define FU740_I2C_1 0x10031000
+
+// Reset Vector - 4
+#define FU740_ROM1 0x00001000
+// After reset vector it will jump directly to this address if ZSBL is used (ZSBL code)
+#define FU740_ROM2 0x00010000
+#define FU740_MSEL FU740_ROM // mode select is always at start of ROM
+
+// naming changed a bit between FU540 and FU740 manuals
+// Ethernet MAC -> Ethernet
+// Ethernet Management -> GEMGXL MGMT
+#define SIFIVE_ETHERNET_MAC  0x10090000
+#define SIFIVE_ETHERNET_MGMT 0x100A0000
+
+#define FU740_UART(i) (FU740_UART0 + 0x1000 * i)
diff --git a/src/soc/sifive/fu740/include/soc/clock.h b/src/soc/sifive/fu740/include/soc/clock.h
new file mode 100644
index 0000000000..01cb1b359a
--- /dev/null
+++ b/src/soc/sifive/fu740/include/soc/clock.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_SIFIVE_FU740_CLOCK_H__
+#define __SOC_SIFIVE_FU740_CLOCK_H__
+
+void clock_init(void);
+int clock_get_pclk(void);
+
+#endif /* __SOC_SIFIVE_FU740_CLOCK_H__ */
diff --git a/src/soc/sifive/fu740/include/soc/gpio.h b/src/soc/sifive/fu740/include/soc/gpio.h
new file mode 100644
index 0000000000..b0466cc8c2
--- /dev/null
+++ b/src/soc/sifive/fu740/include/soc/gpio.h
@@ -0,0 +1,36 @@
+#ifndef _SOC_SIFIVE_FU740_GPIO_H_
+#define _SOC_SIFIVE_FU740_GPIO_H_
+
+#include <stdint.h>
+
+//TODO these are mainboard specific
+enum gpio {
+	J29_1,
+	PMICINTB,
+	PMICSHDN,
+	J8_1,
+	J8_3,
+	PCIE_PWREN, // connected to power rails of PCIe connectors
+	THERM,
+	UBRDG_RSTN,
+	PCIE_PERSTN, // connected to PERST pin of PCIe connectors
+	ULPI_RSTN,
+	J8_2,
+	UHUB_RSTN,
+	GEMGXL_RST,
+	J8_4,
+	EN_VDD_SD,
+	SD_CD,
+};
+
+// this is to satisfy src/include/gpio.h
+typedef enum gpio gpio_t;
+
+enum gpio_direction {
+	GPIO_INPUT,
+	GPIO_OUTPUT,
+};
+
+void gpio_set_direction(gpio_t gpio, enum gpio_direction gpio_dir);
+
+#endif // _SOC_SIFIVE_FU740_GPIO_H_
diff --git a/src/soc/sifive/fu740/include/soc/otp.h b/src/soc/sifive/fu740/include/soc/otp.h
new file mode 100644
index 0000000000..0405fda224
--- /dev/null
+++ b/src/soc/sifive/fu740/include/soc/otp.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_SIFIVE_FU740_OTP_H__
+#define __SOC_SIFIVE_FU740_OTP_H__
+
+#include <stdint.h>
+
+u32 otp_read_word(u16 idx);
+u32 otp_read_serial(void);
+
+#endif /* __SOC_SIFIVE_FU740_OTP_H__ */
diff --git a/src/soc/sifive/fu740/include/soc/sdram.h b/src/soc/sifive/fu740/include/soc/sdram.h
new file mode 100644
index 0000000000..8848d1a587
--- /dev/null
+++ b/src/soc/sifive/fu740/include/soc/sdram.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SIFIVE_COMMON_SDRAM_H
+#define SIFIVE_COMMON_SDRAM_H
+
+#include <stdint.h>
+#include <types.h>
+
+void sdram_init(size_t dram_size);
+size_t sdram_size(void);
+
+#endif
diff --git a/src/soc/sifive/fu740/include/soc/spi.h b/src/soc/sifive/fu740/include/soc/spi.h
new file mode 100644
index 0000000000..5c41019bf5
--- /dev/null
+++ b/src/soc/sifive/fu740/include/soc/spi.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_SIFIVE_FU740_SPI_H__
+#define __SOC_SIFIVE_FU740_SPI_H__
+
+#include <spi-generic.h>
+
+// Frame Format Register (fmt)
+
+#define FU740_SPI_PROTO_S	0 // Data Pins: MOSI MISO
+#define FU740_SPI_PROTO_D	1 // Data Pins: DQ0 DQ1
+#define FU740_SPI_PROTO_Q	2 // Data Pins: DQ0 DQ1 DQ2 DQ3
+
+#define FU740_SPI_ENDIAN_BIG	0 // send MSB first
+#define FU740_SPI_ENDIAN_LITTLE	1 // send LSB first
+
+// Serial Clock Mode Register (sckmode)
+
+#define FU740_SPI_PHA_LOW	0 // inactive state of SCK is logical 0
+#define FU740_SPI_PHA_HIGH	1 // inactive state of SCK is logical 1
+
+#define FU740_SPI_POL_LEADING	0 // data is sampled on leading edge of sck
+#define FU740_SPI_POL_TRAILING	1 // data is sampled on trailing edge of sck
+
+// ffmt register (SPI Flash Instruction Format Register)
+struct fu740_spi_ffmt_config {
+	unsigned int cmd_en;     // enable sending of command
+	unsigned int addr_len;   // number of address bytes (0-4)
+	unsigned int pad_cnt;    // number of dummy cycles
+	unsigned int cmd_proto;  // protocol for transmitting command
+	unsigned int addr_proto; // protocol for transmitting address and padding
+	unsigned int data_proto; // protocol for receiving data bytes
+	unsigned int cmd_code;   // value of command byte
+	unsigned int pad_code;   // first 8 bits to transmit during dummy cycles
+};
+
+struct fu740_spi_fmt_config {
+	unsigned int protocol;   // FU740_SPI_PROTO_S, FU740_SPI_PROTO_D, FU740_SPI_PROTO_Q
+	unsigned int endianness; // 0 = MSB, 1 = LSB
+	unsigned int io_dir;     // Rx, Tx
+	unsigned int bits_per_frame; // up to 8bits
+};
+
+struct fu740_spi_config {
+	unsigned int freq; // speed of spi interface
+	unsigned int pha;  // serial clock phase
+	unsigned int pol;  // serial clock polarity
+	struct fu740_spi_fmt_config fmt_config;   // frame format config
+	struct fu740_spi_ffmt_config ffmt_config; // flash instruction format
+};
+
+extern struct fu740_spi_config fu740_spi_configs[];
+
+int fu740_spi_setup(const struct spi_slave *slave);
+
+#endif /* __SOC_SIFIVE_FU740_SPI_H__ */