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| author | Kane Chen <kane.chen@intel.com> | 2018-08-03 09:39:57 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-06 07:56:47 +0000 |
| commit | c024381f8f1916607a8e5ee209063d17d37a5a61 (patch) | |
| tree | f6e92ccc832c04698bc0a0b1d8d62e4efdafeebf /src/soc/sifive/fu540/cbmem.c | |
| parent | a8b4b75d241b0ae03cc2f11589339515afa41773 (diff) | |
vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config
From doc 571118, the bit 5 of OdtConfig is nWR config.
If the bit 5 is set, MRC will set MR1 nWR field to 24.
If the bit 5 is clear, MRC will set MR1 nWR field to 6.
Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/27814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/sifive/fu540/cbmem.c')
0 files changed, 0 insertions, 0 deletions