rk3288: add spi

BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I858ac723d640dde8538aebb968fcff364fa7207c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8253a9dbad2afdf9eb9a8554fd355e6815887407
Original-Change-Id: Ib6ee7e3092429a3e47b102751ed6a88aeb9ee7d3
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209429
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8859
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

6 files changed, 593 insertions, 44 deletions

diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index 13c811475b..05003a210d 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -26,6 +26,7 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
 bootblock-$(CONFIG_DRIVERS_UART) += uart.c
 endif
 bootblock-y += clock.c
+bootblock-y += spi.c
 
 romstage-y += cbmem.c
 romstage-y += timer.c
@@ -33,10 +34,12 @@ romstage-y += monotonic_timer.c
 romstage-y += media.c
 romstage-$(CONFIG_DRIVERS_UART) += uart.c
 romstage-y += clock.c
+romstage-y += spi.c
 
 ramstage-y += cbmem.c
 ramstage-y += timer.c
 ramstage-y += monotonic_timer.c
 ramstage-y += clock.c
+ramstage-y += spi.c
 ramstage-y += media.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index 3087a1377f..757d180387 100755
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -64,11 +64,17 @@ check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c);
 
 static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE;
 
+#define PLL_DIVISORS(hz, _nr, _no) {\
+	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / 24000000), .no = _no};\
+	_Static_assert(((u64)hz * _nr * _no / 24000000) * 24000000 /\
+			(_nr * _no) == hz,\
+	#hz "Hz cannot be hit with PLL divisors in " __FILE__);
+
 /* apll = 816MHz, gpll = 594MHz, cpll = 384MHz, dpll = 300MHz */
-static const struct pll_div apll_init_cfg = {.nr = 1, .nf = 68, .no = 2};
-static const struct pll_div gpll_init_cfg = {.nr = 2, .nf = 198, .no = 4};
-static const struct pll_div cpll_init_cfg = {.nr = 2, .nf = 128, .no = 4};
-static const struct pll_div dpll_init_cfg = {.nr = 1, .nf = 50, .no = 4};
+static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 2);
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 4);
+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4);
+static const struct pll_div dpll_init_cfg = PLL_DIVISORS(DPLL_HZ, 1, 4);
 
 /*******************PLL CON0 BITS***************************/
 #define PLL_OD_MSK	(0x0F)
@@ -161,21 +167,21 @@ static const struct pll_div dpll_init_cfg = {.nr = 1, .nf = 50, .no = 4};
 static int rkclk_set_pll(u32 *pll_con, const struct pll_div *pll_div_cfg)
 {
 	/* enter rest */
-	writel(RK_SETBITS(PLL_RESET, PLL_RESET_MSK), &pll_con[3]);
+	writel(RK_SETBITS(PLL_RESET_MSK), &pll_con[3]);
 
-	writel(RK_SETBITS((pll_div_cfg->nr - 1) << PLL_NR_SHIFT, PLL_NR_MSK)
-		| RK_SETBITS((pll_div_cfg->no - 1), PLL_OD_MSK), &pll_con[0]);
+	writel(RK_CLRSETBITS(PLL_NR_MSK, (pll_div_cfg->nr - 1) << PLL_NR_SHIFT)
+	      | RK_CLRSETBITS(PLL_OD_MSK, (pll_div_cfg->no - 1)), &pll_con[0]);
 
-	writel(RK_SETBITS((pll_div_cfg->nf - 1), PLL_NF_MSK),
+	writel(RK_CLRSETBITS(PLL_NF_MSK, (pll_div_cfg->nf - 1)),
 		&pll_con[1]);
 
-	writel(RK_SETBITS(((pll_div_cfg->nf >> 1) - 1), PLL_BWADJ_MSK),
+	writel(RK_CLRSETBITS(PLL_BWADJ_MSK, ((pll_div_cfg->nf >> 1) - 1)),
 		&pll_con[2]);
 
 	udelay(10);
 
 	/* return form rest */
-	writel(RK_SETBITS(PLL_RESET_RESUME, PLL_RESET_MSK), &pll_con[3]);
+	writel(RK_CLRBITS(PLL_RESET_MSK), &pll_con[3]);
 
 	return 0;
 }
@@ -183,10 +189,10 @@ static int rkclk_set_pll(u32 *pll_con, const struct pll_div *pll_div_cfg)
 void rkclk_init(void)
 {
 	/* pll enter slow-mode */
-	writel(RK_SETBITS(APLL_MODE_SLOW, APLL_MODE_MSK)
-		| RK_SETBITS(GPLL_MODE_SLOW, GPLL_MODE_MSK)
-		| RK_SETBITS(CPLL_MODE_SLOW, CPLL_MODE_MSK)
-		| RK_SETBITS(DPLL_MODE_SLOW, DPLL_MODE_MSK),
+	writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW)
+		| RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW)
+		| RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW)
+		| RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW),
 		&cru_ptr->cru_mode_con);
 
 	/* init pll */
@@ -212,19 +218,19 @@ void rkclk_init(void)
 	 * core clock select apll, apll clk = 816MHz
 	 * arm clk = 816MHz, mpclk = 204MHz, m0clk = 408MHz
 	 */
-	writel(RK_SETBITS(CORE_SEL_APLL, CORE_SEL_PLL_MSK)
-		| RK_SETBITS(0 << A12_DIV_SHIFT, A12_DIV_MSK)
-		| RK_SETBITS(3 << MP_DIV_SHIFT, MP_DIV_MSK)
-		| RK_SETBITS(1, M0_DIV_MSK),
+	writel(RK_CLRBITS(CORE_SEL_PLL_MSK)
+		| RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT)
+		| RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT)
+		| RK_CLRSETBITS(M0_DIV_MSK, 1 << 0),
 		&cru_ptr->cru_clksel_con[0]);
 
 	/*
 	 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 	 * l2ramclk = 408MHz, atclk = 204MHz, pclk_dbg = 204MHz
 	 */
-	writel(RK_SETBITS(1, L2_DIV_MSK)
-		| RK_SETBITS((3 << ATCLK_DIV_SHIFT), ATCLK_DIV_MSK)
-		| RK_SETBITS((3 << PCLK_DBG_DIV_SHIFT), PCLK_DBG_DIV_MSK),
+	writel(RK_CLRSETBITS(L2_DIV_MSK, 1 << 0)
+		| RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT))
+		| RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT)),
 		&cru_ptr->cru_clksel_con[37]);
 
 	/*
@@ -233,33 +239,44 @@ void rkclk_init(void)
 	 * peri clock select gpll, gpll clk = 594MHz
 	 * aclk = 148.5MHz, hclk = 148.5Mhz, pclk = 74.25MHz
 	 */
-	writel(RK_SETBITS(PERI_SEL_GPLL, PERI_SEL_PLL_MSK)
-		| RK_SETBITS(1 << PERI_PCLK_DIV_SHIFT, PERI_PCLK_DIV_MSK)
-		| RK_SETBITS(0 << PERI_HCLK_DIV_SHIFT, PERI_HCLK_DIV_MSK)
-		| RK_SETBITS(3, PERI_ACLK_DIV_MSK),
+	writel(RK_SETBITS(PERI_SEL_PLL_MSK)
+		| RK_CLRSETBITS(PERI_PCLK_DIV_MSK, 1 << PERI_PCLK_DIV_SHIFT)
+		| RK_CLRSETBITS(PERI_HCLK_DIV_MSK, 0 << PERI_HCLK_DIV_SHIFT)
+		| RK_CLRSETBITS(PERI_ACLK_DIV_MSK, 3 << 0),
 		&cru_ptr->cru_clksel_con[10]);
 
 	/* PLL enter normal-mode */
-	writel(RK_SETBITS(APLL_MODE_NORM, APLL_MODE_MSK)
-		| RK_SETBITS(GPLL_MODE_NORM, GPLL_MODE_MSK)
-		| RK_SETBITS(CPLL_MODE_NORM, CPLL_MODE_MSK)
-		| RK_SETBITS(DPLL_MODE_NORM, DPLL_MODE_MSK),
+	writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM)
+		| RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM)
+		| RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM)
+		| RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM),
 		&cru_ptr->cru_mode_con);
 
 }
 
-void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy)
+void rkclk_configure_spi(unsigned int bus, unsigned int hz)
 {
-	u32 phy_ctl_srstn_shift = 4 + 5 * ch;
-	u32 ctl_psrstn_shift = 3 + 5 * ch;
-	u32 ctl_srstn_shift = 2 + 5 * ch;
-	u32 phy_psrstn_shift = 1 + 5 * ch;
-	u32 phy_srstn_shift = 5 * ch;
-
-	writel(RK_SETBITS(phy << phy_ctl_srstn_shift, 1 << phy_ctl_srstn_shift)
-		| RK_SETBITS(ctl << ctl_psrstn_shift, 1 << ctl_psrstn_shift)
-		| RK_SETBITS(ctl << ctl_srstn_shift, 1 << ctl_srstn_shift)
-		| RK_SETBITS(phy << phy_psrstn_shift, 1 << phy_psrstn_shift)
-		| RK_SETBITS(phy << phy_srstn_shift, 1 << phy_srstn_shift),
-		&cru_ptr->cru_softrst_con[10]);
+	int src_clk_div = GPLL_HZ / hz;
+
+	assert((src_clk_div - 1 < 127) && (src_clk_div * hz == GPLL_HZ));
+
+	switch (bus) {	/*select gpll as spi src clk, and set div*/
+	case 0:
+		writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7
+					     | (src_clk_div - 1) << 0),
+					     &cru_ptr->cru_clksel_con[25]);
+		break;
+	case 1:
+		writel(RK_CLRSETBITS(1 << 15 | 0x1f << 8, 1 << 15
+					      | (src_clk_div - 1) << 8),
+					      &cru_ptr->cru_clksel_con[25]);
+		break;
+	case 2:
+		writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7
+					     | (src_clk_div - 1) << 0),
+					     &cru_ptr->cru_clksel_con[39]);
+		break;
+	default:
+		printk(BIOS_ERR, "do not support this spi bus\n");
+	}
 }
diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h
index cc2ec78d16..e7732199ac 100755
--- a/src/soc/rockchip/rk3288/clock.h
+++ b/src/soc/rockchip/rk3288/clock.h
@@ -22,8 +22,13 @@
 
 #include "addressmap.h"
 
+#define APLL_HZ		816000000
+#define GPLL_HZ		594000000
+#define CPLL_HZ		384000000
+#define DPLL_HZ		300000000
+
 void rkclk_init(void);
-void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
+void rkclk_configure_spi(unsigned int bus, unsigned int hz);
 
 #endif	/* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */
 
diff --git a/src/soc/rockchip/rk3288/cpu.h b/src/soc/rockchip/rk3288/cpu.h
index ed629c975f..c42bbe8752 100644
--- a/src/soc/rockchip/rk3288/cpu.h
+++ b/src/soc/rockchip/rk3288/cpu.h
@@ -20,7 +20,9 @@
 #ifndef __SOC_ROCKCHIP_RK3288_CPU_H__
 #define __SOC_ROCKCHIP_RK3288_CPU_H__
 
-#define RK_SETBITS(val, msk) (((msk) << 16) | (val))
+#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set)
+#define RK_SETBITS(set) RK_CLRSETBITS(0, set)
+#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0)
 
 #endif	/* __SOC_ROCKCHIP_RK3288_CPU_H__ */
 
diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c
new file mode 100755
index 0000000000..396f537a01
--- /dev/null
+++ b/src/soc/rockchip/rk3288/spi.c
@@ -0,0 +1,318 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <spi-generic.h>
+#include <spi_flash.h>
+#include <delay.h>
+#include <timer.h>
+#include <endian.h>
+#include "addressmap.h"
+#include "spi.h"
+#include "clock.h"
+
+struct rockchip_spi_slave {
+	struct spi_slave slave;
+	struct rockchip_spi *regs;
+	unsigned int speed_hz;
+	unsigned int fifo_size;
+};
+
+#define SPI_TIMEOUT_US	1000
+#define SPI_SRCCLK_HZ   99000000
+
+static struct rockchip_spi_slave rockchip_spi_slaves[3] = {
+	{
+	 .slave = {
+		   .bus = 0,
+		   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
+		   },
+	 .regs = (void *)SPI0_BASE,
+	 .speed_hz = 9000000,
+	 .fifo_size = 32,
+	},
+	{
+	 .slave = {.bus = 1, .rw = SPI_READ_FLAG,},
+	 .regs = (void *)SPI1_BASE,
+	 .speed_hz = 11000000,
+	 .fifo_size = 32,
+	},
+	{
+	 .slave = {
+		   .bus = 2,
+		   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
+		   },
+	 .regs = (void *)SPI2_BASE,
+	 .speed_hz = 11000000,
+	 .fifo_size = 32,
+	},
+
+};
+
+static struct rockchip_spi_slave *to_rockchip_spi(struct spi_slave *slave)
+{
+	return container_of(slave, struct rockchip_spi_slave, slave);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
+{
+	assert(bus >= 0 && bus < 3);
+	return &(rockchip_spi_slaves[bus].slave);
+}
+
+static void spi_cs_activate(struct spi_slave *slave)
+{
+	struct rockchip_spi *regs = to_rockchip_spi(slave)->regs;
+	setbits_le32(&regs->ser, 1);
+}
+
+static void spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct rockchip_spi *regs = to_rockchip_spi(slave)->regs;
+	clrbits_le32(&regs->ser, 1);
+}
+
+static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable)
+{
+	if (enable == 1)
+		writel(1, &regs->spienr);
+	else
+		writel(0, &regs->spienr);
+}
+
+static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
+{
+	unsigned short clk_div = 0;
+
+	/* Calculate clock divisor.  */
+	clk_div = SPI_SRCCLK_HZ / hz;
+	clk_div = (clk_div + 1) & 0xfffe;
+	assert((clk_div - 1) * hz == SPI_SRCCLK_HZ);
+	writel(clk_div, &regs->baudr);
+}
+
+void rockchip_spi_init(unsigned int bus)
+{
+	struct rockchip_spi_slave *espi = &rockchip_spi_slaves[bus];
+	struct rockchip_spi *regs = espi->regs;
+	unsigned int ctrlr0 = 0;
+
+	rkclk_configure_spi(bus, SPI_SRCCLK_HZ);
+	rockchip_spi_enable_chip(regs, 0);
+	rockchip_spi_set_clk(regs, espi->speed_hz);
+
+	/* Operation Mode */
+	ctrlr0 = (SPI_OMOD_MASTER << SPI_OMOD_OFFSET);
+
+	/* Data Frame Size */
+	ctrlr0 |= SPI_DFS_8BIT << SPI_DFS_OFFSET;
+
+	/* Chip Select Mode */
+	ctrlr0 |= (SPI_CSM_KEEP << SPI_CSM_OFFSET);
+
+	/* SSN to Sclk_out delay */
+	ctrlr0 |= (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET);
+
+	/* Serial Endian Mode */
+	ctrlr0 |= (SPI_SEM_LITTLE << SPI_SEM_OFFSET);
+
+	/* First Bit Mode */
+	ctrlr0 |= (SPI_FBM_MSB << SPI_FBM_OFFSET);
+
+	/* Byte and Halfword Transform */
+	ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET);
+
+	/* Rxd Sample Delay */
+	ctrlr0 |= (0 << SPI_RXDSD_OFFSET);
+
+	/* Frame Format */
+	ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET);
+
+	writel(ctrlr0, &regs->ctrlr0);
+
+	/*fifo depth */
+	writel(espi->fifo_size / 2 - 1, &regs->txftlr);
+	writel(espi->fifo_size / 2 - 1, &regs->rxftlr);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	spi_cs_activate(slave);
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	spi_cs_deactivate(slave);
+}
+
+static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs)
+{
+	struct mono_time start;
+	struct rela_time rt;
+	timer_monotonic_get(&start);
+	do {
+		if (!(readl(&regs->sr) & SR_BUSY))
+			return 0;
+		rt = current_time_from(&start);
+	} while (rela_time_in_microseconds(&rt) < SPI_TIMEOUT_US);
+	printk(BIOS_DEBUG,
+	       "RK SPI: Status keeps busy for 1000us after a read/write!\n");
+	return -1;
+}
+
+int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int sout,
+	     void *din, unsigned int sin)
+{
+	unsigned int len;
+	unsigned int bytes_remaining;
+	uint8_t *p;
+	struct rockchip_spi *regs = to_rockchip_spi(slave)->regs;
+	struct rockchip_spi_slave *espi = to_rockchip_spi(slave);
+
+	if (dout) {
+		len = sout;
+		p = (uint8_t *) dout;
+		bytes_remaining = len;
+		writel(0, &regs->spienr);	/*disable spi */
+		writel(len - 1, &regs->ctrlr1);	/*wrtie len */
+
+		/*tx only */
+		clrsetbits_le32(&regs->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET,
+					      SPI_TMOD_TO << SPI_TMOD_OFFSET);
+		writel(1, &regs->spienr);/*enable spi */
+		while (bytes_remaining) {
+			if ((readl(&regs->txflr) & 0x3f)
+			    < espi->fifo_size) {
+				writel(*p++, &regs->txdr);
+				bytes_remaining--;
+			}
+		}
+		if (rockchip_spi_wait_till_not_busy(regs))
+			return -1;
+	}
+	if (din) {
+		len = sin;
+		p = (uint8_t *) din;
+		writel(0, &regs->spienr);	/*disable spi */
+		writel(len - 1, &regs->ctrlr1);	/*write len */
+
+		/*rx only */
+		clrsetbits_le32(&regs->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET,
+					      SPI_TMOD_RO << SPI_TMOD_OFFSET);
+		while (len) {
+			writel(0, &regs->spienr);/*disable spi */
+			bytes_remaining = MIN(len, 0xffff);
+			writel(bytes_remaining - 1, &regs->ctrlr1);
+			len -= bytes_remaining;
+			writel(1, &regs->spienr);/*enable spi */
+			while (bytes_remaining) {
+				if (readl(&regs->rxflr) & 0x3f) {
+					*p = readl(&regs->rxdr) & 0xff;
+					p += 1;
+					bytes_remaining--;
+				}
+			}
+		}
+		if (rockchip_spi_wait_till_not_busy(regs))
+			return -1;
+	}
+	return 0;
+}
+
+static int rockchip_spi_read(struct spi_slave *slave, void *dest, uint32_t len,
+			     uint32_t off)
+{
+	unsigned int cmd;
+
+	spi_claim_bus(slave);
+	cmd = swab32(off) | SF_READ_DATA_CMD;
+	if (spi_xfer(slave, &cmd, sizeof(cmd), dest, len)) {
+		printk(BIOS_DEBUG, "rockchip_spi_read err\n");
+		spi_release_bus(slave);
+		return -1;
+	}
+	spi_release_bus(slave);
+	return len;
+}
+
+struct rockchip_spi_media {
+	struct spi_slave *slave;
+	struct cbfs_simple_buffer buffer;
+};
+
+static int rockchip_spi_cbfs_open(struct cbfs_media *media)
+{
+	return 0;
+}
+
+static int rockchip_spi_cbfs_close(struct cbfs_media *media)
+{
+	return 0;
+}
+
+static size_t rockchip_spi_cbfs_read(struct cbfs_media *media, void *dest,
+				     size_t offset, size_t count)
+{
+	struct rockchip_spi_media *spi =
+	    (struct rockchip_spi_media *)media->context;
+
+	return rockchip_spi_read(spi->slave, dest, count, offset);
+}
+
+static void *rockchip_spi_cbfs_map(struct cbfs_media *media, size_t offset,
+				   size_t count)
+{
+	struct rockchip_spi_media *spi =
+	    (struct rockchip_spi_media *)media->context;
+
+	count = ALIGN_UP(count, 4);
+
+	return cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
+}
+
+static void *rockchip_spi_cbfs_unmap(struct cbfs_media *media,
+				     const void *address)
+{
+	struct rockchip_spi_media *spi =
+	    (struct rockchip_spi_media *)media->context;
+	return cbfs_simple_buffer_unmap(&spi->buffer, address);
+}
+
+int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media,
+				       void *buffer_address, size_t buffer_size)
+{
+	static struct rockchip_spi_media context;
+	static struct rockchip_spi_slave *eslave = &rockchip_spi_slaves[2];
+	context.slave = &eslave->slave;
+	context.buffer.allocated = context.buffer.last_allocate = 0;
+	context.buffer.buffer = buffer_address;
+	context.buffer.size = buffer_size;
+	media->context = (void *)&context;
+	media->open = rockchip_spi_cbfs_open;
+	media->close = rockchip_spi_cbfs_close;
+	media->read = rockchip_spi_cbfs_read;
+	media->map = rockchip_spi_cbfs_map;
+	media->unmap = rockchip_spi_cbfs_unmap;
+
+	return 0;
+}
diff --git a/src/soc/rockchip/rk3288/spi.h b/src/soc/rockchip/rk3288/spi.h
new file mode 100755
index 0000000000..c6880c2b23
--- /dev/null
+++ b/src/soc/rockchip/rk3288/spi.h
@@ -0,0 +1,204 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3288_SPI_H__
+#define __SOC_ROCKCHIP_RK3288_SPI_H__
+
+/* This driver serves as a CBFS media source. */
+#include <cbfs.h>
+#include <spi-generic.h>
+#include <stdint.h>
+
+struct rockchip_spi {
+	u32  ctrlr0;
+	u32  ctrlr1;
+	u32  spienr;
+	u32  ser;
+	u32  baudr;
+	u32  txftlr;
+	u32  rxftlr;
+	u32  txflr;
+	u32  rxflr;
+	u32  sr;
+	u32  ipr;
+	u32  imr;
+	u32  isr;
+	u32  risr;
+	u32  icr;
+	u32  dmacr;
+	u32  damtdlr;
+	u32  damrdlr;
+	u32  reserved[(0x400-0x48)/4];
+	u32  txdr[0x100];
+	u32  rxdr[0x100];
+};
+check_member(rockchip_spi, rxdr, 0x800);
+
+
+#define SF_READ_DATA_CMD	0x3
+
+/* --------Bit fields in CTRLR0--------begin */
+
+#define SPI_DFS_OFFSET	0	/* Data Frame Size */
+#define SPI_DFS_MASK	0x3
+#define SPI_DFS_4BIT	0x00
+#define SPI_DFS_8BIT	0x01
+#define SPI_DFS_16BIT	0x02
+#define SPI_DFS_RESV	0x03
+
+/* Control Frame Size */
+#define SPI_CFS_OFFSET	2
+#define SPI_CFS_MASK	0xF
+
+/* Serial Clock Phase */
+#define SPI_SCPH_OFFSET	6
+#define SPI_SCPH_MASK	0x1
+
+/* Serial clock toggles in middle of first data bit */
+#define SPI_SCPH_TOGMID	0
+
+/* Serial clock toggles at start of first data bit */
+#define SPI_SCPH_TOGSTA	1
+
+/* Serial Clock Polarity */
+#define SPI_SCOL_OFFSET	7
+#define SPI_SCOL_MASK	0x1
+
+/* Inactive state of clock serial clock is low */
+#define SPI_SCOL_LOW	0
+
+/* Inactive state of clock serial clock is high */
+#define SPI_SCOL_HIGH	1
+
+/* Chip Select Mode */
+#define SPI_CSM_OFFSET	8
+#define SPI_CSM_MASK	0x3
+
+/* ss_n keep low after every frame data is transferred */
+#define SPI_CSM_KEEP	0x00
+
+/*
+ * ss_n be high for half sclk_out cycles after
+ * every frame data is transferred
+ */
+#define SPI_CSM_HALF	0x01
+
+/* ss_n be high for one sclk_out cycle after every frame data is transferred */
+#define SPI_CSM_ONE	0x02
+#define SPI_CSM_RESV	0x03
+
+/* SSN to Sclk_out delay */
+#define SPI_SSN_DELAY_OFFSET	10
+#define SPI_SSN_DELAY_MASK	0x1
+/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */
+#define SPI_SSN_DELAY_HALF	0x00
+/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */
+#define SPI_SSN_DELAY_ONE	0x01
+
+/* Serial Endian Mode */
+#define SPI_SEM_OFFSET	11
+#define SPI_SEM_MASK	0x1
+/* little endian */
+#define SPI_SEM_LITTLE	0x00
+/* big endian */
+#define SPI_SEM_BIG	0x01
+
+/* First Bit Mode */
+#define SPI_FBM_OFFSET	12
+#define SPI_FBM_MASK	0x1
+/* first bit in MSB */
+#define SPI_FBM_MSB	0x00
+/* first bit in LSB */
+#define SPI_FBM_LSB	0x01
+
+/* Byte and Halfword Transform */
+#define SPI_HALF_WORLD_TX_OFFSET 13
+#define SPI_HALF_WORLD_MASK	0x1
+/* apb 16bit write/read, spi 8bit write/read */
+#define SPI_APB_16BIT	0x00
+/* apb 8bit write/read, spi 8bit write/read */
+#define SPI_APB_8BIT	0x01
+
+/* Rxd Sample Delay */
+#define SPI_RXDSD_OFFSET	14
+#define SPI_RXDSD_MASK	0x3
+
+/* Frame Format */
+#define SPI_FRF_OFFSET	16
+#define SPI_FRF_MASK	0x3
+/* motorola spi */
+#define SPI_FRF_SPI	0x00
+/* Texas Instruments SSP*/
+#define SPI_FRF_SSP	0x01
+/*  National Semiconductors Microwire */
+#define SPI_FRF_MICROWIRE	0x02
+#define SPI_FRF_RESV	0x03
+
+/* Transfer Mode */
+#define SPI_TMOD_OFFSET	18
+#define SPI_TMOD_MASK	0x3
+/* xmit & recv */
+#define	SPI_TMOD_TR	0x00
+/* xmit only */
+#define SPI_TMOD_TO	0x01
+/* recv only */
+#define SPI_TMOD_RO	0x02
+#define SPI_TMOD_RESV	0x03
+
+/* Operation Mode */
+#define SPI_OMOD_OFFSET	20
+#define SPI_OMOD_MASK	0x1
+/* Master Mode */
+#define	SPI_OMOD_MASTER	0x00
+/* Slave Mode */
+#define SPI_OMOD_SLAVE	0x01
+
+/* --------Bit fields in CTRLR0--------end */
+/* Bit fields in SR, 7 bits */
+#define SR_MASK	0x7f
+#define SR_BUSY	(1 << 0)
+#define SR_TF_FULL	(1 << 1)
+#define SR_TF_EMPT	(1 << 2)
+#define SR_RF_EMPT	(1 << 3)
+#define SR_RF_FULL	(1 << 4)
+
+/* Bit fields in ISR, IMR, RISR, 7 bits */
+#define SPI_INT_TXEI	(1 << 0)
+#define SPI_INT_TXOI	(1 << 1)
+#define SPI_INT_RXUI	(1 << 2)
+#define SPI_INT_RXOI	(1 << 3)
+#define SPI_INT_RXFI	(1 << 4)
+
+/* Bit fields in DMACR */
+#define SPI_DMACR_TX_ENABLE	(1 << 1)
+#define SPI_DMACR_RX_ENABLE	(1 << 0)
+
+/* Bit fields in ICR */
+#define SPI_CLEAR_INT_ALL	(1 << 0)
+#define SPI_CLEAR_INT_RXUI	(1 << 1)
+#define SPI_CLEAR_INT_RXOI	(1 << 2)
+#define SPI_CLEAR_INT_TXOI	(1 << 3)
+
+/* Serve as CBFS media source */
+int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media,
+				     void *buffer_address,
+				     size_t buffer_size);
+void rockchip_spi_init(unsigned int bus);
+
+#endif