diff options
| author | Prasad Malisetty <quic_pmaliset@quicinc.com> | 2022-07-25 13:35:05 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2022-08-01 18:04:54 +0000 |
| commit | 78298f5c8f46c6615655b2711a76b61bf8218378 (patch) | |
| tree | 24ffa5ce577bcf30f712c49ed8cc1dc305be8af2 /src/soc/qualcomm/sc7280/include | |
| parent | a47a4906353f8d534b0ce1d573082008decb8697 (diff) | |
soc/qualcomm/sc7280: Enable PCIe driver
Enable PCIe functionality on sc7280 and supply all the needed data
for PCIe generic platform driver.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I1f79a0ae2dea594d6026d55a15978eeb92a8ff18
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66148
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/sc7280/include')
| -rw-r--r-- | src/soc/qualcomm/sc7280/include/soc/addressmap.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 31f409ff4c..31f7d64f8f 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -68,4 +68,27 @@ #define QMP_PHY_PCS_REG_BASE 0x088e9c00 #define USB_HOST_DWC3_BASE 0x0a60c100 +/* PCIE_1 */ +#define PCIE1_PCIE_PARF 0x01C08000 +#define PCIE1_GEN3X2_PCIE_DBI 0x40000000 +#define PCIE1_GEN3X2_PCIE_ELBI 0x40000F20 +#define PCIE1_GEN3X2_DWC_PCIE_DM_IATU 0x40001000 +#define PCIE1_SPACE_END_ADDR 0x60000000 +#define PCIE1_BCR 0x18D000 + +/* QMP PCIE_1 PHY */ +#define PCIE_1_QMP_PHY 0x01C0E000 + +/* QMP PHY, Serdes,Tx, Rx and PCS register definitions */ +#define PCIE1_QMP_PHY_PCS_COM 0x01C0EA00 +#define PCE1_QPHY_SERDES 0x01C0E000 +#define PCE1_QPHY_TX0 0x01C0E200 +#define PCE1_QPHY_RX0 0x01C0E400 +#define PCE1_QPHY_TX1 0x01C0E600 +#define PCE1_QPHY_RX1 0x01C0E800 +#define PCE1_QPHY_PCS_MISC 0x01C0EE00 + +/* PHY BCR */ +#define GCC_PCIE_1_PHY_BCR 0x18E01C + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ |