diff options
| author | Taniya Das <tdas@codeaurora.org> | 2019-03-28 16:54:15 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-23 18:00:52 +0000 |
| commit | 3ee485741bede7535377ef10516596524f8008a8 (patch) | |
| tree | c3a741856d359cf4adf6f9f068a409aa1b5ae2bf /src/soc/qualcomm/qcs405/clock.c | |
| parent | 27fbbcffc53d1a4df8b47aaa50c85f85c93b8e40 (diff) | |
qcs405: clock: Update SPI API
Update SPI enable/disable and configure clock
API for supporting all the blsp and qup for qcs405.
Change-Id: I39622571cb671f62312283a010129ceecb654f61
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/qualcomm/qcs405/clock.c')
| -rw-r--r-- | src/soc/qualcomm/qcs405/clock.c | 101 |
1 files changed, 78 insertions, 23 deletions
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 369bcdf531..ebad13b721 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -209,11 +209,38 @@ void clock_configure_uart(uint32_t hz) clock_configure(uart_clk, uart_cfg, hz, ARRAY_SIZE(uart_cfg)); } -void clock_configure_spi(int blsp, uint32_t hz) +void clock_configure_spi(int blsp, int qup, uint32_t hz) { - struct qcs405_clock *spi_clk = (blsp == 1) ? - (struct qcs405_clock *)&gcc->blsp1_qup4_spi_clk - : (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + struct qcs405_clock *spi_clk = 0; + + if (blsp == 1) { + switch (qup) { + case 0: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup0_spi_clk; + break; + case 1: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup1_spi_clk; + break; + case 2: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup2_spi_clk; + break; + case 3: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup3_spi_clk; + break; + case 4: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup4_spi_clk; + break; + } + } else if (blsp == 2) + spi_clk = (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg)); } @@ -228,38 +255,66 @@ void clock_disable_uart(void) clock_disable(&gcc->blsp1_uart2_apps_cbcr); } -void clock_enable_spi(int blsp) +void clock_enable_spi(int blsp, int qup) { - (blsp == 1) ? clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr) - : clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + if (blsp == 1) { + switch (qup) { + case 0: + clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr); + break; + case 1: + clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr); + break; + case 2: + clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr); + break; + case 3: + clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr); + break; + case 4: + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + break; + } + } else if (blsp == 2) + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); } -void clock_disable_spi(int blsp) +void clock_disable_spi(int blsp, int qup) { - (blsp == 1) ? clock_disable(&gcc->blsp1_qup4_spi_apps_cbcr) - : clock_disable(&gcc->blsp2_qup0_spi_apps_cbcr); + if (blsp == 1) { + switch (qup) { + case 0: + clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr); + break; + case 1: + clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr); + break; + case 2: + clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr); + break; + case 3: + clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr); + break; + case 4: + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + break; + } + } else if (blsp == 2) + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); + } void clock_init(void) { - clock_configure_gpll0(); - - clock_configure(&gcc->blsp1_uart2_apps_clk, uart_cfg, 1843200, - ARRAY_SIZE(uart_cfg)); - - clock_enable(&gcc->blsp1_uart2_apps_cbcr); clock_enable_vote(&gcc->blsp1_ahb_cbcr, &gcc->gcc_apcs_clock_branch_en_vote, BLSP1_AHB_CLK_ENA); - clock_configure(&gcc->blsp1_qup4_spi_clk, spi_cfg, 1000000, - ARRAY_SIZE(spi_cfg)); - clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); - - clock_configure(&gcc->blsp2_qup0_spi_clk, spi_cfg, 50000000, - ARRAY_SIZE(spi_cfg)); - clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); clock_enable_vote(&gcc->blsp2_ahb_cbcr, &gcc->gcc_apcs_clock_branch_en_vote, BLSP2_AHB_CLK_ENA); |