diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-06-23 10:41:38 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-04 00:15:50 +0100 |
| commit | 0b70bd13363b560039788f60e1bdd5f3727f489c (patch) | |
| tree | 61a44e1ef70255851ffcaee6ca33c9b80e07d6e3 /src/soc/qualcomm/ipq806x | |
| parent | 6b33286e958780f52216d9b787158c9598671b88 (diff) | |
ipq806x: move GPIO definitions to the proper include file
When the IPQ SPI driver was ported to coreboot, a few GPIO related
definitions ended up in a wrong include file. Move them to the proper
place and get rid of duplicated definition of GPIO_OUT.
BUG=chrome-os-partner:27784, chrome-os-partner:29871
TEST=proto0 still boots with the new firmware
Original-Change-Id: I4b06067a71c85efaf0e48f29e232f83fd1f725a8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205328
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit df73bb0023f5eaf5594ef41b3632c4402ebf126c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I109e62e3bfc9bd15640ff697be7634f42435a3e4
Reviewed-on: http://review.coreboot.org/8058
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/qualcomm/ipq806x')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/gpio.h | 8 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/spi.h | 8 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/spi.c | 4 |
3 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/qualcomm/ipq806x/include/gpio.h b/src/soc/qualcomm/ipq806x/include/gpio.h index efaf30e996..c1cefd4a8b 100644 --- a/src/soc/qualcomm/ipq806x/include/gpio.h +++ b/src/soc/qualcomm/ipq806x/include/gpio.h @@ -35,6 +35,14 @@ typedef unsigned int gpio_t; +#define GPIO_FUNC_ENABLE 1 +#define GPIO_FUNC_DISABLE 0 +#define FUNC_SEL_1 1 +#define FUNC_SEL_3 3 +#define FUNC_SEL_GPIO 0 +#define GPIO_DRV_STR_10MA 0x4 +#define GPIO_DRV_STR_11MA 0x7 + /* GPIO TLMM: Direction */ #define GPIO_INPUT 0 #define GPIO_OUTPUT 1 diff --git a/src/soc/qualcomm/ipq806x/include/spi.h b/src/soc/qualcomm/ipq806x/include/spi.h index 48073fadd0..f7dda07a51 100644 --- a/src/soc/qualcomm/ipq806x/include/spi.h +++ b/src/soc/qualcomm/ipq806x/include/spi.h @@ -229,14 +229,6 @@ #define GSBI7_SPI_MISO 7 #define GSBI7_SPI_MOSI 6 -#define GPIO_FUNC_ENABLE 1 -#define GPIO_FUNC_DISABLE 0 -#define FUNC_SEL_1 1 -#define FUNC_SEL_3 3 -#define FUNC_SEL_GPIO 0 -#define GPIO_DRV_STR_10MA 0x4 -#define GPIO_DRV_STR_11MA 0x7 -#define GPIO_OUT 1 #define MSM_GSBI_MAX_FREQ 51200000 #define SPI_RESET_STATE 0 diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 52d11c19c4..f1a180ba88 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -277,9 +277,9 @@ static void CS_change(int port_num, int cs_num, int enable) uint32_t addr = GPIO_IN_OUT_ADDR(cs_gpio); uint32_t val = readl_i(addr); - val &= (~(1 << GPIO_OUT)); + val &= (~(1 << GPIO_OUTPUT)); if (!enable) - val |= (1 << GPIO_OUT); + val |= (1 << GPIO_OUTPUT); writel_i(val, addr); } |