diff options
author | Patrick Georgi <pgeorgi@chromium.org> | 2015-06-22 19:41:29 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-30 21:43:01 +0200 |
commit | 40a3e321d4e8f2877de1700db67b8c7f7ea89820 (patch) | |
tree | b8270b2ceb9e290d2e4e9a99868acb9cd335de6f /src/soc/nvidia/tegra210/romstage.c | |
parent | 7f641e68f25c0b79960a97a6b265851c46298aae (diff) |
nvidia/tegra210: add new SoC
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.
Change-Id: I81853434600390d643160fe57554495b2bfe60ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/romstage.c')
-rw-r--r-- | src/soc/nvidia/tegra210/romstage.c | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c new file mode 100644 index 0000000000..c029e937b3 --- /dev/null +++ b/src/soc/nvidia/tegra210/romstage.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/exception.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/cbmem_console.h> +#include <console/console.h> +#include <program_loading.h> +#include <soc/addressmap.h> +#include <soc/ccplex.h> +#include <soc/clock.h> +#include <soc/sdram.h> +#include <soc/sdram_configs.h> +#include <soc/romstage.h> +#include <soc/nvidia/tegra/apbmisc.h> +#include <timer.h> +#include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void __attribute__((weak)) romstage_mainboard_init(void) +{ + /* Default empty implementation. */ +} + +void romstage(void) +{ + console_init(); + exception_init(); + + printk(BIOS_INFO, "T210: romstage here\n"); + +#if CONFIG_BOOTROM_SDRAM_INIT + printk(BIOS_INFO, "T210 romstage: SDRAM init done by BootROM, RAMCODE = %d\n", + sdram_get_ram_code()); +#else + sdram_init(get_sdram_config()); + printk(BIOS_INFO, "T210 romstage: sdram_init done\n"); +#endif + + /* + * IMPORTANT: + * DO NOT INITIALIZE ANY CARVEOUT BEFORE TZ. + * + * Trust Zone needs to be initialized after the DRAM initialization + * because carveout registers are programmed during DRAM init. + * cbmem_initialize() is dependent on the Trust Zone region + * initalization because CBMEM lives right below the Trust Zone which + * needs to be properly identified. + */ + trustzone_region_init(); + + gpu_region_init(); + + /* + * When romstage is running it's always on the reboot path -- never a + * resume path where cbmem recovery is required. Therefore, always + * initialize the cbmem area to be empty. + */ + cbmem_initialize_empty(); + + ccplex_cpu_prepare(); + printk(BIOS_INFO, "T210 romstage: cpu prepare done\n"); + + romstage_mainboard_init(); + + run_ramstage(); +} + +void platform_prog_run(struct prog *prog) +{ + ccplex_cpu_start(prog_entry(prog)); + + clock_halt_avp(); +} |