tegra132: separate/refactor clock enable/reset code

Added distinct functions for clock_enable and clock_clear_reset,
and rewrote clock_enable_clear_reset() to use them. Useful when
unpowergating SOR partition, for instance, where we need to
enable a bunch of periph clocks, unclamp SOR, then take all of
those periphs out of reset.

BUG=none
BRANCH=none
TEST=none, built rush/ryu OK.

Change-Id: I92edf3104adc8eb7637c47a5e000788fd55f1452
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fd76a6d0d0fb7922c6beacbc1cfcb365b6537b2
Original-Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212916
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8991
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h
index 6f98e3c618..494f28d4db 100644
--- a/src/soc/nvidia/tegra132/include/soc/clock.h
+++ b/src/soc/nvidia/tegra132/include/soc/clock.h
@@ -292,6 +292,8 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
 		 u32 same_freq);
 void clock_cpu0_config(void);
 void clock_halt_avp(void);
+void clock_enable(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
+void clock_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
 void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
 void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg);
 void clock_reset_l(u32 l);