soc/mediatek/mt8196: Enable lastbus debug hardware

Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded.

The watchdog cannot clear it and it will be printed out on the serial
console for bus hanging analysis.

TEST=build pass, and check log with:
[INFO ]  ******************* MT8196 lastbus ******************
[INFO ]  --- debug_ctrl_ao_APINFRA_IO_AO 0x10155000 37 ---
[INFO ]  00402504
[INFO ]  c34b00d6
[INFO ]  61804050
[INFO ]  00051840
[INFO ]  10401610

BUG=b:317009620

Signed-off-by: Xiwen Shao <xiwen.shao@mediatek.corp-partner.google.com>
Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>

4 files changed, 164 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 559b8a1bb2..3a1d103a8e 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -13,6 +13,7 @@ all-y += ../common/uart.c
 bootblock-y += bootblock.c
 bootblock-y += ../common/bootblock.c bootblock.c
 bootblock-y += ../common/early_init.c
+bootblock-y += ../common/lastbus_v2.c lastbus.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c
index 19b90eee45..578d353e39 100644
--- a/src/soc/mediatek/mt8196/bootblock.c
+++ b/src/soc/mediatek/mt8196/bootblock.c
@@ -2,6 +2,7 @@
 
 #include <bootblock_common.h>
 #include <soc/early_init.h>
+#include <soc/lastbus_v2.h>
 #include <soc/mmu_operations.h>
 #include <soc/pll.h>
 #include <soc/wdt.h>
@@ -9,6 +10,7 @@
 void bootblock_soc_init(void)
 {
 	mtk_mmu_init();
+	lastbus_init();
 	mtk_wdt_init();
 	mt_pll_init();
 	mt_pll_post_init();
diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h
index 73702bf73e..24cea8fb0f 100644
--- a/src/soc/mediatek/mt8196/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h
@@ -6,6 +6,7 @@
 enum {
 	MCUSYS_BASE		= 0x0C000000,
 	MCUPM_CFG_BASE		= 0x0C240000,
+	BUS_TRACE_MONITOR_BASE	= 0x0D040000,
 	IO_PHYS			= 0x10000000,
 };
 
@@ -35,11 +36,20 @@ enum {
 	BCRM_INFRA_AO_BASE	= IO_PHYS + 0x00022000,
 	BCRM_INFRA1_AO_BASE	= IO_PHYS + 0x0002A000,
 	GPIO_BASE		= IO_PHYS + 0x0002D000,
+	DBGSYS_AO_DEBUG_BASE	= IO_PHYS + 0x00031000,
+	APINFRA_IO_AO_DEBUG_BASE	= IO_PHYS + 0x00155000,
 	APINFRA_IO_CTRL_AO_BCRM_BASE	= IO_PHYS + 0x00156000,
+	APINFRA_IO_CTRL_AO_DEBUG_BASE	= IO_PHYS + 0x00157000,
 	DRAMC_CHA_AO_BASE	= IO_PHYS + 0x00230000,
+	APINFRA_DRAMC_AO_DEBUG_BASE	= IO_PHYS + 0x002F1000,
 	EMI0_BASE		= IO_PHYS + 0x00469000,
 	EMI0_MPU_BASE		= IO_PHYS + 0x00468000,
+	NEMI_AO_DEBUG_BASE	= IO_PHYS + 0x00416000,
+	SEMI_AO_DEBUG_BASE	= IO_PHYS + 0x00516000,
 	EMI1_BASE		= IO_PHYS + 0x00569000,
+	APINFRA_EMI_AO_DEBUG_BASE	= IO_PHYS + 0x00611000,
+	EMI_INFRA_AO_DEBUG_BASE		= IO_PHYS + 0x00644000,
+	APINFRA_BIG4_AO_DEBUG_BASE	= IO_PHYS + 0x00691000,
 	DPM_PM_SRAM_BASE	= IO_PHYS + 0x00900000,
 	DPM_DM_SRAM_BASE	= IO_PHYS + 0x00920000,
 	DPM_CFG_BASE		= IO_PHYS + 0x00940000,
@@ -75,12 +85,21 @@ enum {
 	I2C8_BASE		= IO_PHYS + 0x03B30000,
 	I2C9_BASE		= IO_PHYS + 0x03BB0000,
 	IMP_IIC_WRAP_N_BASE	= IO_PHYS + 0x03C30000,
+	APINFRA_IO_INTF_AO_DEBUG_BASE	= IO_PHYS + 0x04011000,
 	APINFRA_IO_NOC_AO_BCRM_BASE	= IO_PHYS + 0x04012000,
+	APINFRA_MEM_INTF_AO_DEBUG_BASE	= IO_PHYS + 0x04031000,
 	APINFRA_MEM_NOC_AO_BCRM_BASE	= IO_PHYS + 0x04032000,
+	APINFRA_INT_AO_DEBUG_BASE	= IO_PHYS + 0x04051000,
+	APINFRA_MMU_AO_DEBUG_BASE	= IO_PHYS + 0x04071000,
+	APINFRA_SLB_AO_DEBUG_BASE	= IO_PHYS + 0x04091000,
+	APINFRA_MEM_AO_DEBUG_BASE	= IO_PHYS + 0x04116000,
 	APINFRA_MEM_CTRL_AO_BCRM_BASE	= IO_PHYS + 0x04124000,
+	APINFRA_MEM_CTRL_AO_DEBUG_BASE	= IO_PHYS + 0x04125000,
 	APIFRBUS_AO_MEM_REG_BASE	= IO_PHYS + 0x04126000,
 	THERM_CTRL_BASE		= IO_PHYS + 0x04414000,
 	VOTE_BASE		= IO_PHYS + 0x04500000,
+	DBG_TRACKER_BASE	= IO_PHYS + 0x04780000,
+	INFRA_TRACKER_BASE	= IO_PHYS + 0x047A0000,
 	UART0_BASE		= IO_PHYS + 0x06000000,
 	SPI0_BASE		= IO_PHYS + 0x06110000,
 	SPI1_BASE		= IO_PHYS + 0x06130000,
@@ -113,11 +132,13 @@ enum {
 	PERI_PAR_BCRM_BASE	= IO_PHYS + 0x06610000,
 	PERICFG_AO_SEC_BASE	= IO_PHYS + 0x06630000,
 	PERICFG_AO_BASE		= IO_PHYS + 0x06640000,
+	PERI_PAR_AO_DEBUG_BASE	= IO_PHYS + 0x06680000,
 	SSUSB_IPPC_BASE		= IO_PHYS + 0x06703E00,
 	SSUSB_SIF_BASE		= IO_PHYS + 0x06730300,
 	USB_BUS_BCRM_BASE	= IO_PHYS + 0x06781000,
 	UFSHCI_BASE		= IO_PHYS + 0x06810000,
 	SSR_TOP_BASE		= IO_PHYS + 0x08000000,
+	APINFRA_SSR_AO_DEBUG_BASE	= IO_PHYS + 0x080F1000,
 	VLPCFG_BASE		= IO_PHYS + 0x0C001000,
 	SCP_BASE		= IO_PHYS + 0x0C004000,
 	SCP_PBUS_BASE		= IO_PHYS + 0x0C00D000,
@@ -128,7 +149,9 @@ enum {
 	PMIF_SPMI_BASE		= IO_PHYS + 0x0C01A000,
 	SPMI_MST_BASE		= IO_PHYS + 0x0C01C000,
 	SPMI_MST_P_BASE		= IO_PHYS + 0x0C01C800,
+	VLP_AO_DEBUG_BASE	= IO_PHYS + 0x0C031000,
 	SYSTIMER_BASE		= IO_PHYS + 0x0C400000,
+	VLP_TRACKER_BASE        = IO_PHYS + 0x0C4E0000,
 	MMVOTE_MMSYS_CONFIG_BASE	= IO_PHYS + 0x12000000,
 	MMVOTE_MMSYS1_CONFIG_BASE	= IO_PHYS + 0x12400000,
 	MMVOTE_OVLSYS_CONFIG_BASE	= IO_PHYS + 0x12800000,
@@ -143,6 +166,7 @@ enum {
 	MMVOTE_CAM_MAIN_R1A_BASE	= IO_PHYS + 0x1A000000,
 	MMVOTE_CCU_MAIN_BASE		= IO_PHYS + 0x1C800000,
 	MMVOTE_DISP_VDISP_AO_CONFIG_BASE	= IO_PHYS + 0x1E800000,
+	MMUP_AO_DEBUG_BASE      = IO_PHYS + 0x21A22000,
 	MMVOTE_BASE		= IO_PHYS + 0x21B00000,
 	MMPC_BASE		= IO_PHYS + 0x21B50000,
 	MMSYS_CONFIG_BASE	= IO_PHYS + 0x22000000,
diff --git a/src/soc/mediatek/mt8196/lastbus.c b/src/soc/mediatek/mt8196/lastbus.c
new file mode 100644
index 0000000000..6e2f032ae1
--- /dev/null
+++ b/src/soc/mediatek/mt8196/lastbus.c
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/lastbus_v2.h>
+
+static const struct lastbus_monitor monitors[] = {
+	{
+		.name = "debug_ctrl_ao_DBGSYS_AO",
+		.base = DBGSYS_AO_DEBUG_BASE,
+		.num_ports = 1,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_IO_AO",
+		.base = APINFRA_IO_AO_DEBUG_BASE,
+		.num_ports = 37,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_IO_CTRL_AO",
+		.base = APINFRA_IO_CTRL_AO_DEBUG_BASE,
+		.num_ports = 3,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_DRAMC_AO",
+		.base = APINFRA_DRAMC_AO_DEBUG_BASE,
+		.num_ports = 11,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_EMI_AO",
+		.base = APINFRA_EMI_AO_DEBUG_BASE,
+		.num_ports = 15,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_BIG4_AO",
+		.base = APINFRA_BIG4_AO_DEBUG_BASE,
+		.num_ports = 13,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_IO_INTF_AO",
+		.base = APINFRA_IO_INTF_AO_DEBUG_BASE,
+		.num_ports = 33,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_MEM_INTF_AO",
+		.base = APINFRA_MEM_INTF_AO_DEBUG_BASE,
+		.num_ports = 42,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_INT_AO",
+		.base = APINFRA_INT_AO_DEBUG_BASE,
+		.num_ports = 7,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_MMU_AO",
+		.base = APINFRA_MMU_AO_DEBUG_BASE,
+		.num_ports = 8,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_SLB_AO",
+		.base = APINFRA_SLB_AO_DEBUG_BASE,
+		.num_ports = 8,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_MEM_AO",
+		.base = APINFRA_MEM_AO_DEBUG_BASE,
+		.num_ports = 26,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_MEM_CTRL_AO",
+		.base = APINFRA_MEM_CTRL_AO_DEBUG_BASE,
+		.num_ports = 2,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_APINFRA_SSR_AO",
+		.base = APINFRA_SSR_AO_DEBUG_BASE,
+		.num_ports = 5,
+		.bus_freq_mhz = 26,
+	},
+	{
+		.name = "debug_ctrl_ao_NEMI_AO",
+		.base = NEMI_AO_DEBUG_BASE,
+		.num_ports = 18,
+		.bus_freq_mhz = 800,
+	},
+	{
+		.name = "debug_ctrl_ao_SEMI_AO",
+		.base = SEMI_AO_DEBUG_BASE,
+		.num_ports = 18,
+		.bus_freq_mhz = 800,
+	},
+	{
+		.name = "debug_ctrl_ao_EMI_INFRA_AO",
+		.base = EMI_INFRA_AO_DEBUG_BASE,
+		.num_ports = 70,
+		.bus_freq_mhz = 800,
+	},
+	{
+		.name = "debug_ctrl_ao_PERI_PAR_AO",
+		.base = PERI_PAR_AO_DEBUG_BASE,
+		.num_ports = 27,
+		.bus_freq_mhz = 78,
+	},
+	{
+		.name = "debug_ctrl_ao_VLP_AO",
+		.base = VLP_AO_DEBUG_BASE,
+		.num_ports = 17,
+		.bus_freq_mhz = 156,
+	},
+	{
+		.name = "debug_ctrl_ao_MMUP_AO",
+		.base = MMUP_AO_DEBUG_BASE,
+		.num_ports = 25,
+		.bus_freq_mhz = 728,
+	},
+};
+
+const struct lastbus_config lastbus_cfg = {
+	.latch_platform = "MT8196",
+	.timeout_ms = 200,
+	.timeout_type = 0,
+	.num_used_monitors = ARRAY_SIZE(monitors),
+	.monitors = monitors,
+};