summaryrefslogtreecommitdiff
path: root/src/soc/mediatek
diff options
context:
space:
mode:
authorSubrata Banik <subratabanik@google.com>2022-01-31 21:55:51 +0530
committerSubrata Banik <subratabanik@google.com>2022-02-04 12:23:39 +0000
commit526cc3ed44aacdad7a03ba7009baebbca2a308e8 (patch)
treed9d8ad6ba02787fe70e4d12cd3e99aac5b8360c5 /src/soc/mediatek
parentebd75315b47619895725878682f84d0ae120e2c2 (diff)
soc/intel/{adl, common}: Add routines into CSE IA-common code
This patch adds routines to keep CSE and other HECI devices into the lower power device state (AKA D0I3). - cse_set_to_d0i3 => Set CSE device state to D0I3 - heci_set_to_d0i3 => Function sets D0I3 for all HECI devices Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI device count info from SoC layer to common CSE block. As per PCH EDS, the HECI device count for various SoCs are: ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4) APL => 1 (CSE) SKL/Xeon_SP => 5 (CSE, IDE-R, KT, CSE2 and CSE3) BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/mediatek')
0 files changed, 0 insertions, 0 deletions