soc/mediatek/mt8196: Enable MMU operation for L2C SRAM and DMA

- Turn off L2C SRAM and reconfigure as L2 cache:
  Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
  After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
  the L2C SRAM as L2 cache.

- Configure DMA buffer in DRAM:
  Set DRAM DMA to be non-cacheable to load blob correctly.

TEST=build pass, register(disable_l2c) read ok
BUG=b:317009620

Change-Id: I6a3cb63d3418f085f5d8d08b282dd59ea431c294
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83925
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 96aea39986..44fa59e927 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -13,8 +13,12 @@ bootblock-y += ../common/mmu_operations.c
 
 romstage-y += ../common/cbmem.c
 romstage-y += emi.c
+romstage-y += l2c_ops.c
+romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 
 ramstage-y += emi.c
+ramstage-y += l2c_ops.c
+ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 ramstage-y += soc.c
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8196/include