diff options
| author | Tim Crawford <tcrawford@system76.com> | 2024-02-27 09:41:43 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-03-04 14:53:18 +0000 |
| commit | daa4fb2ca2cab566e6a1c01f6edda65b34e2d4b9 (patch) | |
| tree | 33a8970301190eec80cdd002e16571cedc40ddf0 /src/soc/mediatek/mt8173/rtc.c | |
| parent | 8b495c2706e3e033d65a123f101e75284762219e (diff) | |
mb/system76/adl,rpl: Enable PchHdaSdiEnable
Commit 4a58d14506ef ("soc/intel/alderlake: Hook up UPD PchHdaSdiEnable")
and commit 2d482386182e ("soc/intel/alderlake: Set PchHdaSdiEnable for
Alder Lake") hooked up this UPD in devicetree, causing the FSP default
to be overridden (now disabled by default).
Enable SDI to fix the following error:
[DEBUG] PCI: 00:00:1f.3 init
[DEBUG] azalia_audio: base = 0xbfbcc000
[DEBUG] azalia_audio: No codec!
[DEBUG] PCI: 00:00:1f.3 init finished in 5 msecs
Tested on gaze17-3050: Speaker output works again.
Change-Id: Iceac1faec939ce9eea68c335929f96ec5f2bd132
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/soc/mediatek/mt8173/rtc.c')
0 files changed, 0 insertions, 0 deletions