soc/mediatek: Include sdram_info in ddr_base_info

Sync dramc_param.h with private repo mtk-dramk (CL:*3751861).

BUG=none
TEST=emerge-asurada coreboot
TEST=Hayato boots with fast calibration
BRANCH=asurada

Change-Id: I79541f66ce68a75147c22b83a456e6268ca1485e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

1 files changed, 21 insertions, 22 deletions

diff --git a/src/soc/mediatek/common/include/soc/dramc_param.h b/src/soc/mediatek/common/include/soc/dramc_param.h
index e809379261..00bf7c0431 100644
--- a/src/soc/mediatek/common/include/soc/dramc_param.h
+++ b/src/soc/mediatek/common/include/soc/dramc_param.h
@@ -4,8 +4,8 @@
 #define __SOC_MEDIATEK_DRAMC_PARAM_H__
 
 /*
- * This file is shared between coreboot and dram blob. Any change in this file
- * should be synced to the other repository.
+ * NOTE: This file is shared between coreboot and dram blob. Any change in this
+ * file should be synced to the other repository.
  */
 
 #include <stdint.h>
@@ -27,21 +27,21 @@ enum DRAMC_PARAM_STATUS_CODES {
 	DRAMC_ERR_FAST_CALIBRATION,
 };
 
-enum DRAMC_PARAM_DVFS_FLAG {
-	DRAMC_DISABLE_DVFS,
-	DRAMC_ENABLE_DVFS,
-};
-
 enum DRAMC_PARAM_FLAGS {
 	DRAMC_FLAG_HAS_SAVED_DATA = 0x0001,
 };
 
-enum DRAMC_PARAM_DDR_TYPE {
+enum SDRAM_DVFS_FLAG {
+	DRAMC_DISABLE_DVFS,
+	DRAMC_ENABLE_DVFS,
+};
+
+enum SDRAM_DDR_TYPE {
 	DDR_TYPE_DISCRETE,
 	DDR_TYPE_EMCP,
 };
 
-enum DRAMC_PARAM_GEOMETRY_TYPE {
+enum SDRAM_DDR_GEOMETRY_TYPE {
 	DDR_TYPE_2CH_2RK_4GB_2_2,
 	DDR_TYPE_2CH_2RK_6GB_3_3,
 	DDR_TYPE_2CH_2RK_8GB_4_4_BYTE,
@@ -50,10 +50,10 @@ enum DRAMC_PARAM_GEOMETRY_TYPE {
 	DDR_TYPE_2CH_2RK_8GB_4_4,
 };
 
-enum DRAM_PARAM_VOLTAGE_TYPE {
-	DRAM_VOLTAGE_NVCORE_NVDRAM,
-	DRAM_VOLTAGE_HVCORE_HVDRAM,
-	DRAM_VOLTAGE_LVCORE_LVDRAM,
+enum SDRAM_VOLTAGE_TYPE {
+	SDRAM_VOLTAGE_NVCORE_NVDRAM,
+	SDRAM_VOLTAGE_HVCORE_HVDRAM,
+	SDRAM_VOLTAGE_LVCORE_LVDRAM,
 };
 
 struct dramc_param_header {
@@ -63,6 +63,11 @@ struct dramc_param_header {
 	u16 flags;	/* DRAMC_PARAM_FLAGS, update in the dram blob */
 };
 
+struct sdram_info {
+	u32 ddr_type;			/* SDRAM_DDR_TYPE */
+	u32 ddr_geometry;		/* SDRAM_DDR_GEOMETRY_TYPE */
+};
+
 struct sdram_params {
 	u32 rank_num;
 	u16 num_dlycell_perT;
@@ -118,10 +123,9 @@ struct emi_mdl {
 };
 
 struct ddr_base_info {
-	u32 config_dvfs;		/* DRAMC_PARAM_DVFS_FLAG */
-	u32 ddr_type;			/* DRAMC_PARAM_DDR_TYPE */
-	u32 ddr_geometry;		/* DRAMC_PARAM_GEOMETRY_TYPE */
-	u32 voltage_type;		/* DRAM_PARAM_VOLTAGE_TYPE */
+	u32 config_dvfs;		/* SDRAM_DVFS_FLAG */
+	struct sdram_info sdram;
+	u32 voltage_type;		/* SDRAM_VOLTAGE_TYPE */
 	u32 support_ranks;
 	u64 rank_size[RANK_MAX];
 	struct emi_mdl emi_config;
@@ -139,11 +143,6 @@ struct dramc_param {
 	struct dramc_data dramc_datas;
 };
 
-struct sdram_info {
-	u32 ddr_geometry;		/* DRAMC_PARAM_GEOMETRY_TYPE */
-	u32 ddr_type;			/* DRAMC_PARAM_DDR_TYPE */
-};
-
 const struct sdram_info *get_sdram_config(void);
 struct dramc_param *get_dramc_param_from_blob(void *blob);
 void dump_param_header(const void *blob);