diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-04-20 13:10:47 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-27 12:31:58 +0000 |
| commit | c2570dc99800070d987bda05c33113930a506fd6 (patch) | |
| tree | 4436407078c20a32f7f51f90f6b96028793769d1 /src/soc/intel | |
| parent | f021952c40673c3b66f39ae8fea8db7265bdfff3 (diff) | |
soc/intel/alderlake: Implement PMC soft strap interface lock
This patch performs locking of the PMC soft strap message interface.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS. Verified Bit 0 of PMC
MMIO register 0x104c is set as below.
> localhost ~ # iotools mmio_read32 0xfe00104c
0x00000001
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/lockdown.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index 5d012d8e1b..f018dbd28d 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -24,8 +24,10 @@ static void pmc_lockdown_cfg(int chipset_lockdown) if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK); - if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) + if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK); + setbits32(pmcbase + SSML, SSML_SSL_EN); + } } void soc_lockdown_config(int chipset_lockdown) |