diff options
| author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-07-31 14:46:41 +0800 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-11 20:15:10 +0000 |
| commit | ec886ec6fad3d34f6a9d22ab39871434cefdd219 (patch) | |
| tree | 35888ecfd9949f98711cbd1688065d1561f7b5cc /src/soc/intel | |
| parent | f2a59a4de2440f8f1dc4a33d031471f1902c362d (diff) | |
xeon_sp/cpx: Enable PCH thermal device via FSP
Tested=On OCP Delta Lake, OpenBMC sensor-util can see PCH Temp readings.
Change-Id: I39d0d0a982476f9fece51cfa19dcbd0da5dea690
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44075
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/romstage.c | 7 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 71c68cf885..17f801ba74 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -92,6 +92,8 @@ #define XHCI_BUS_NUMBER 0x0 #define PCH_DEV_SLOT_XHCI 0x14 +#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2) + #define XHCI_FUNC_NUM 0x0 #define HPET_BUS_NUM 0x0 diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 96949fd8af..6c65994412 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -3,6 +3,7 @@ #include <arch/romstage.h> #include <fsp/api.h> #include <soc/romstage.h> +#include <soc/pci_devs.h> #include "chip.h" void __weak mainboard_memory_init_params(FSPM_UPD *mupd) @@ -13,6 +14,7 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSPM_CONFIG *m_cfg = &mupd->FspmConfig; + const struct device *dev; /* ErrorLevel - 0 (disable) to 8 (verbose) */ m_cfg->DebugPrintLevel = 8; @@ -61,5 +63,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) m_cfg->PEXPHIDE = 0x0; m_cfg->HidePEXPMenu = 0x0; + /* Enable PCH thermal device in FSP, the definition of ThermalDeviceEnable is + 0: Disable, 1: Enabled in PCI mode, 2: Enabled in ACPI mode */ + dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + m_cfg->ThermalDeviceEnable = dev && dev->enabled; + mainboard_memory_init_params(mupd); } |