soc/intel: Factor out common smbus.h

Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 46 insertions, 172 deletions

diff --git a/src/soc/intel/alderlake/include/soc/smbus.h b/src/soc/intel/alderlake/include/soc/smbus.h
index ab4994aa37..c865fbe94e 100644
--- a/src/soc/intel/alderlake/include/soc/smbus.h
+++ b/src/soc/intel/alderlake/include/soc/smbus.h
@@ -1,35 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 6
- */
+#ifndef _SOC_SMBUS_H_
+#define _SOC_SMBUS_H_
 
-#ifndef _SOC_ALDERLAKE_SMBUS_H_
-#define _SOC_ALDERLAKE_SMBUS_H_
-
-/* IO and MMIO registers under primary BAR */
-
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
-#define TCO1_STS			0x04
-#define  TCO_TIMEOUT			(1 << 3)
-#define TCO2_STS			0x06
-#define  TCO_STS_SECOND_TO		(1 << 1)
-#define  TCO_INTRD_DET			(1 << 0)
-#define TCO1_CNT			0x08
-#define  TCO_LOCK			(1 << 12)
-#define  TCO_TMR_HLT			(1 << 11)
-#define TCO2_CNT			0x0A
-#define  TCO_INTRD_SEL_MASK		(3 << 1)
-#define  TCO_INTRD_SEL_SMI		(1 << 2)
-#define  TCO_INTRD_SEL_INT		(1 << 1)
-
-/*
- * Default slave address value for PCH. This value is set to match default
- * value set by hardware. It is useful since PCH is able to respond even
- * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
- */
-#define SMBUS_SLAVE_ADDR		0x44
+#include <intelpch/smbus.h>
 
 #endif
diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h
index c6d20a50d1..c865fbe94e 100644
--- a/src/soc/intel/cannonlake/include/soc/smbus.h
+++ b/src/soc/intel/cannonlake/include/soc/smbus.h
@@ -1,27 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef _SOC_CANNONLAKE_SMBUS_H_
-#define _SOC_CANNONLAKE_SMBUS_H_
+#ifndef _SOC_SMBUS_H_
+#define _SOC_SMBUS_H_
 
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
-#define TCO1_STS			0x04
-#define  TCO_TIMEOUT			(1 << 3)
-#define TCO2_STS			0x06
-#define  TCO_STS_SECOND_TO		(1 << 1)
-#define  TCO_INTRD_DET			(1 << 0)
-#define TCO1_CNT			0x08
-#define  TCO_LOCK			(1 << 12)
-#define  TCO_TMR_HLT			(1 << 11)
-#define TCO2_CNT			0x0A
-#define  TCO_INTRD_SEL_MASK		(3 << 1)
-#define  TCO_INTRD_SEL_SMI		(1 << 2)
-#define  TCO_INTRD_SEL_INT		(1 << 1)
-
-/*
- * Default slave address value for PCH. This value is set to match default
- * value set by hardware. It is useful since PCH is able to respond even
- * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
- */
-#define SMBUS_SLAVE_ADDR		0x44
+#include <intelpch/smbus.h>
 
 #endif
diff --git a/src/soc/intel/common/pch/include/intelpch/smbus.h b/src/soc/intel/common/pch/include/intelpch/smbus.h
new file mode 100644
index 0000000000..238da2b73b
--- /dev/null
+++ b/src/soc/intel/common/pch/include/intelpch/smbus.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _INTELPCH_SMBUS_H_
+#define _INTELPCH_SMBUS_H_
+
+/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
+#define TCO1_STS			0x04
+#define  TCO_TIMEOUT			(1 << 3)
+#define TCO2_STS			0x06
+#define  TCO_STS_SECOND_TO		(1 << 1)
+#define  TCO_INTRD_DET			(1 << 0)
+#define TCO1_CNT			0x08
+#define  TCO_LOCK			(1 << 12)
+#define  TCO_TMR_HLT			(1 << 11)
+#define TCO2_CNT			0x0A
+#define  TCO_INTRD_SEL_MASK		(3 << 1)
+#define  TCO_INTRD_SEL_SMI		(1 << 2)
+#define  TCO_INTRD_SEL_INT		(1 << 1)
+
+/*
+ * Default slave address value for PCH. This value is set to match default
+ * value set by hardware. It is useful since PCH is able to respond even
+ * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
+ */
+#define SMBUS_SLAVE_ADDR		0x44
+
+#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/smbus.h b/src/soc/intel/elkhartlake/include/soc/smbus.h
index 0ea469c8c9..c865fbe94e 100644
--- a/src/soc/intel/elkhartlake/include/soc/smbus.h
+++ b/src/soc/intel/elkhartlake/include/soc/smbus.h
@@ -1,29 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef _SOC_ELKHARTLAKE_SMBUS_H_
-#define _SOC_ELKHARTLAKE_SMBUS_H_
+#ifndef _SOC_SMBUS_H_
+#define _SOC_SMBUS_H_
 
-/* IO and MMIO registers under primary BAR */
-
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
-#define TCO1_STS			0x04
-#define  TCO_TIMEOUT			(1 << 3)
-#define TCO2_STS			0x06
-#define  TCO_STS_SECOND_TO		(1 << 1)
-#define  TCO_INTRD_DET			(1 << 0)
-#define TCO1_CNT			0x08
-#define  TCO_LOCK			(1 << 12)
-#define  TCO_TMR_HLT			(1 << 11)
-#define TCO2_CNT			0x0A
-#define  TCO_INTRD_SEL_MASK		(3 << 1)
-#define  TCO_INTRD_SEL_SMI		(1 << 2)
-#define  TCO_INTRD_SEL_INT		(1 << 1)
-
-/*
- * Default slave address value for PCH. This value is set to match default
- * value set by hardware. It is useful since PCH is able to respond even
- * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
- */
-#define SMBUS_SLAVE_ADDR		0x44
+#include <intelpch/smbus.h>
 
 #endif
diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h
index c8503d5bce..c865fbe94e 100644
--- a/src/soc/intel/icelake/include/soc/smbus.h
+++ b/src/soc/intel/icelake/include/soc/smbus.h
@@ -1,27 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef _SOC_ICELAKE_SMBUS_H_
-#define _SOC_ICELAKE_SMBUS_H_
+#ifndef _SOC_SMBUS_H_
+#define _SOC_SMBUS_H_
 
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
-#define TCO1_STS			0x04
-#define  TCO_TIMEOUT			(1 << 3)
-#define TCO2_STS			0x06
-#define  TCO_STS_SECOND_TO		(1 << 1)
-#define  TCO_INTRD_DET			(1 << 0)
-#define TCO1_CNT			0x08
-#define  TCO_LOCK			(1 << 12)
-#define  TCO_TMR_HLT			(1 << 11)
-#define TCO2_CNT			0x0A
-#define  TCO_INTRD_SEL_MASK		(3 << 1)
-#define  TCO_INTRD_SEL_SMI		(1 << 2)
-#define  TCO_INTRD_SEL_INT		(1 << 1)
-
-/*
- * Default slave address value for PCH. This value is set to match default
- * value set by hardware. It is useful since PCH is able to respond even
- * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
- */
-#define SMBUS_SLAVE_ADDR		0x44
+#include <intelpch/smbus.h>
 
 #endif
diff --git a/src/soc/intel/jasperlake/include/soc/smbus.h b/src/soc/intel/jasperlake/include/soc/smbus.h
index 7a3a890b1d..c865fbe94e 100644
--- a/src/soc/intel/jasperlake/include/soc/smbus.h
+++ b/src/soc/intel/jasperlake/include/soc/smbus.h
@@ -1,29 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef _SOC_JASPERLAKE_SMBUS_H_
-#define _SOC_JASPERLAKE_SMBUS_H_
+#ifndef _SOC_SMBUS_H_
+#define _SOC_SMBUS_H_
 
-/* IO and MMIO registers under primary BAR */
-
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
-#define TCO1_STS			0x04
-#define  TCO_TIMEOUT			(1 << 3)
-#define TCO2_STS			0x06
-#define  TCO_STS_SECOND_TO		(1 << 1)
-#define  TCO_INTRD_DET			(1 << 0)
-#define TCO1_CNT			0x08
-#define  TCO_LOCK			(1 << 12)
-#define  TCO_TMR_HLT			(1 << 11)
-#define TCO2_CNT			0x0A
-#define  TCO_INTRD_SEL_MASK		(3 << 1)
-#define  TCO_INTRD_SEL_SMI		(1 << 2)
-#define  TCO_INTRD_SEL_INT		(1 << 1)
-
-/*
- * Default slave address value for PCH. This value is set to match default
- * value set by hardware. It is useful since PCH is able to respond even
- * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
- */
-#define SMBUS_SLAVE_ADDR		0x44
+#include <intelpch/smbus.h>
 
 #endif
diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h
index bd86aca20a..c865fbe94e 100644
--- a/src/soc/intel/skylake/include/soc/smbus.h
+++ b/src/soc/intel/skylake/include/soc/smbus.h
@@ -3,25 +3,6 @@
 #ifndef _SOC_SMBUS_H_
 #define _SOC_SMBUS_H_
 
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
-#define TCO1_STS			0x04
-#define  TCO_TIMEOUT			(1 << 3)
-#define TCO2_STS			0x06
-#define  TCO_STS_SECOND_TO		(1 << 1)
-#define  TCO_INTRD_DET			(1 << 0)
-#define TCO1_CNT			0x08
-#define  TCO_LOCK			(1 << 12)
-#define  TCO_TMR_HLT			(1 << 11)
-#define TCO2_CNT			0x0A
-#define  TCO_INTRD_SEL_MASK		(3 << 1)
-#define  TCO_INTRD_SEL_SMI		(1 << 2)
-#define  TCO_INTRD_SEL_INT		(1 << 1)
-
-/*
- * Default slave address value for PCH. This value is set to match default
- * value set by hardware. It is useful since PCH is able to respond even
- * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
- */
-#define SMBUS_SLAVE_ADDR		0x44
+#include <intelpch/smbus.h>
 
 #endif
diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h
index 71c4d6a03b..c865fbe94e 100644
--- a/src/soc/intel/tigerlake/include/soc/smbus.h
+++ b/src/soc/intel/tigerlake/include/soc/smbus.h
@@ -1,35 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 6
- */
+#ifndef _SOC_SMBUS_H_
+#define _SOC_SMBUS_H_
 
-#ifndef _SOC_TIGERLAKE_SMBUS_H_
-#define _SOC_TIGERLAKE_SMBUS_H_
-
-/* IO and MMIO registers under primary BAR */
-
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
-#define TCO1_STS			0x04
-#define  TCO_TIMEOUT			(1 << 3)
-#define TCO2_STS			0x06
-#define  TCO_STS_SECOND_TO		(1 << 1)
-#define  TCO_INTRD_DET			(1 << 0)
-#define TCO1_CNT			0x08
-#define  TCO_LOCK			(1 << 12)
-#define  TCO_TMR_HLT			(1 << 11)
-#define TCO2_CNT			0x0A
-#define  TCO_INTRD_SEL_MASK		(3 << 1)
-#define  TCO_INTRD_SEL_SMI		(1 << 2)
-#define  TCO_INTRD_SEL_INT		(1 << 1)
-
-/*
- * Default slave address value for PCH. This value is set to match default
- * value set by hardware. It is useful since PCH is able to respond even
- * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
- */
-#define SMBUS_SLAVE_ADDR		0x44
+#include <intelpch/smbus.h>
 
 #endif