diff options
| author | Kane Chen <kane.chen@intel.corp-partner.google.com> | 2021-11-16 09:07:16 +0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2021-11-23 09:21:16 +0000 |
| commit | 3c01123abb43f5bb35d2bf84f1dfa45b6a297ca3 (patch) | |
| tree | e982807937c3945c641e83597dd33ff2c1be2f1d /src/soc/intel | |
| parent | d88d2da813889b4cdb4bc73492a0ca280667905b (diff) | |
soc/intel/alderlake: remove tmp bar assignment for cpu crashlog
When the cpu_cl_discovery is called, coreboot actually assigns a BAR
to cpu crashlog pci device. Hence, we don't need to assign a tmp BAR
for cpu crashlog pci device
BUG=b:195327879
TEST=Found BERT table is created and the tcss function is ok in depthcharge
Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/crashlog.c | 17 |
1 files changed, 2 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c index 9435aa092d..3a857c1a2b 100644 --- a/src/soc/intel/alderlake/crashlog.c +++ b/src/soc/intel/alderlake/crashlog.c @@ -210,27 +210,14 @@ bool cpu_cl_discovery(void) m_cpu_crashLog_support = true; - /* Program BAR address and enable command register memory space decoding */ - u32 tmp_bar_addr = PCH_PWRM_BASE_ADDRESS; - printk(BIOS_DEBUG, "tmp_bar_addr: 0x%X\n", tmp_bar_addr); - - if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { - pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, tmp_bar_addr); - } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { - pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, tmp_bar_addr); - } else { - printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n", - cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); - return false; - } - pci_or_config16(SA_DEV_TMT, PCI_COMMAND, PCI_COMMAND_MEMORY); + const struct resource *res = find_resource(SA_DEV_TMT, PCI_BASE_ADDRESS_0); + printk(BIOS_DEBUG, "cpu crashlog bar addr: 0x%llX\n", res->base); if (!cpu_cl_gen_discovery_table()) { printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n"); m_cpu_crashLog_present = false; return false; } - m_cpu_crashLog_present = true; return true; } |