diff options
| author | Gang Chen <gang.c.chen@intel.com> | 2024-07-11 06:51:43 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-09-13 11:09:50 +0000 |
| commit | 2f56049778bc98b0d215763c4f1d5d6bb6412e9f (patch) | |
| tree | 1001380b4198233a2bdfce7d8bbc6e5b328ca7a1 /src/soc/intel | |
| parent | 95cf9c0052234cf19599c03ea214eff4a6ed3b65 (diff) | |
soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZE
For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR,
this default size is enough. Use the default size so that more
CAR spaces could be saved for other purpose.
Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84302
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/xeon_sp/gnr/Kconfig | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig index 790f20e012..fae9d8d5ee 100644 --- a/src/soc/intel/xeon_sp/gnr/Kconfig +++ b/src/soc/intel/xeon_sp/gnr/Kconfig @@ -56,15 +56,6 @@ config DCACHE_RAM_SIZE and/or romstage. FSP-T reserves the upper 0x100 for FspReservedBuffer. -config DCACHE_BSP_STACK_SIZE - hex - default 0x60000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. It needs to include FSP-M stack requirement and - CB romstage stack requirement. The integration documentation - says this needs to be 256KiB. - config FSP_M_RC_HEAP_SIZE hex default 0x142000 |