diff options
| author | Hannah Williams <hannah.williams@intel.com> | 2018-01-09 18:23:40 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-15 09:14:35 +0000 |
| commit | cf45830982ff3fb5321970b8271ffc7022ecf8f2 (patch) | |
| tree | c53889ef55a0ad4c7d74e6ee222122d26ee0bd15 /src/soc/intel | |
| parent | 7ee05eddf184764de8aa1e015936a42d069893f2 (diff) | |
soc/intel/{glk,apl} and mainboards: Configure LPC_CLKRUN# pin as GPIO for S0ix
This pin does not have a native function for eSPI. Nonetheless if we use
eSPI, it should be configured as a GPIO and kept unconnected to allow
S0ix entry.
Also removed initialization of LPC pins in mainboard code as they are
already initialized in chipset code. The settings fpr LPC pins in
chipset code were updated to those that were previously in mainboard
code and have been validated on LPC flavor of Geminilake RVP.
BUG=b:79251613
BRANCH=none
TEST=From kernel prompt in bip, type powerd_dbus_suspend.
Check on EC console that SOC enters S0ix.
Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23742
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/lpc.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 70b29b5a42..451aa736d1 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -47,9 +47,9 @@ static const struct pad_config lpc_gpios[] = { #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) #if !IS_ENABLED(CONFIG_SOC_ESPI) PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, UP_20K, DEEP, NF1, HIZCRx1, + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKOUT0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, UP_20K, DEEP, NF1, HIZCRx1, + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKOUT1 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD0 */ @@ -59,10 +59,17 @@ static const struct pad_config lpc_gpios[] = { DISPUPD), /* LPC_AD2 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD3 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_154, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_CLKRUNB */ + PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1), /* LPC_CLKRUNB */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_FRAMEB*/ + DISPUPD), /* LPC_FRAMEB */ +#else + /* + * LPC_CLKRUNB should be in GPIO mode for eSPI. Other pin settings + * i.e. Rx path enable/disable, Tx path enable/disable, pull up + * enable/disable etc are ignored. Leaving this pin in Native mode + * will keep LPC Controller awake and prevent S0ix entry + */ + PAD_NC(GPIO_154, NONE), #endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */ #else PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), |