diff options
| author | John Su <john_su@compal.corp-partner.google.com> | 2019-02-14 17:24:17 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-18 20:27:37 +0000 |
| commit | c94631718b16e027e7ab80006dca494bdb52bb63 (patch) | |
| tree | 77cbf1ac18ce0a07b90e604de8486128c8e3a038 /src/soc/intel | |
| parent | 0790030735b6703e9e512551e4de3f19faa1f4d3 (diff) | |
mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1
Follow b:123461432#5 to update GPIO H3(CNVI_EN#) for DVT1.
Update setting GPIO H3 to output and low level.
BUG=b:123461432
TEST=Built and tested on sarien system
Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions