soc/intel/cannonlake: Add Whiskeylake SoC kconfig

This patch performs below tasks

1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.

2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.

3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.

* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC

4. Add correct FSP blobs path for WHL SoC based designs.

Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

3 files changed, 26 insertions, 8 deletions

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 0a1cff0938..cd8819d2cc 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -3,13 +3,33 @@ config SOC_INTEL_CANNONLAKE
 	help
 	  Intel Cannonlake support
 
-config SOC_INTEL_COFFEELAKE
+config SOC_INTEL_COMMON_CANNONLAKE_BASE
 	bool
 	default n
 	select SOC_INTEL_CANNONLAKE
 	help
+	  Single Kconfig option to select common base Cannonlake support.
+	  This Kconfig will help to select majority of CNL SoC features.
+	  Major difference that exist today between
+	  SOC_INTEL_COMMON_CANNONLAKE_BASE and SOC_INTEL_CANNONLAKE Kconfig
+	  are in FSP Header Files. Hence this Kconfig might help to select
+	  required SoC support FSP headers. Any future Intel SoC would
+	  like to make use of CNL support might just select this Kconfig.
+
+config SOC_INTEL_COFFEELAKE
+	bool
+	default n
+	select SOC_INTEL_COMMON_CANNONLAKE_BASE
+	help
 	  Intel Coffeelake support
 
+config SOC_INTEL_WHISKEYLAKE
+	bool
+	default n
+	select SOC_INTEL_COMMON_CANNONLAKE_BASE
+	help
+	  Intel Whiskeylake support
+
 config SOC_INTEL_CANNONLAKE_PCH_H
 	bool
 	default n
@@ -244,12 +264,12 @@ endchoice
 
 config FSP_HEADER_PATH
 	string "Location of FSP headers"
-	default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if !SOC_INTEL_COFFEELAKE
-	default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE
+	default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
+	default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/"
 
 config FSP_FD_PATH
 	string
 	depends on FSP_USE_REPO
-	default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE
+	default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
 
 endif
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index f312c6f2ea..cb9ad3827f 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -36,8 +36,6 @@
 #include <soc/gpio_defs.h>
 #endif
 
-
-
 struct soc_intel_cannonlake_config {
 
 	/* Common struct containing soc config data required by common code */
@@ -109,7 +107,7 @@ struct soc_intel_cannonlake_config {
 	enum {
 		SaGv_Disabled,
 		SaGv_FixedLow,
-#if !IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
+#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE)
 		SaGv_FixedMid,
 #endif
 		SaGv_FixedHigh,
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index bdaa4afaf1..b8b2c1798c 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -53,7 +53,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 		m_cfg->VmxEnable = 0;
 	else
 		m_cfg->VmxEnable = config->VmxEnable;
-#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE)
 	m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
 #endif