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authorSubrata Banik <subratabanik@google.com>2023-01-20 12:33:58 +0530
committerFelix Held <felix-coreboot@felixheld.de>2023-01-22 00:32:39 +0000
commit84d812cafef4c508883b09b6c5d1a908432ac77a (patch)
treedd47ee00fec630bf7655a4756027ffc8be873d40 /src/soc/intel
parent6d03f8986d0498d04fcf304cb247a60ef506d540 (diff)
soc/intel/apollolake: Add PMC macros for common code usage
This patch adds new macros (i.e. SUS Power Failure and Power Failure) from the APL EDS vol 1 (doc 569262) to be able to implement common code API to clear the power failure status bits. Note: as per the EDS those newly added power management failure bits are RO and shouldn't change any functionality of the existing APL SoC code. The reason behind adding those macro definitions is to fix the compilation issue due to code change targeted for the Intel SKL and Xeon-SP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0bbf11ada2b2f8735173be69ad157b8055021126 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72130 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/include/soc/pm.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index ff5d567d47..dc1419f35a 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -156,15 +156,18 @@
#define COLD_BOOT_STS (1 << 27)
#define COLD_RESET_STS (1 << 26)
#define WARM_RESET_STS (1 << 25)
-#define GLOBAL_RESET_STS (1 << 24)
+#define GBL_RST_STS (1 << 24)
#define SRS (1 << 20)
#define MS4V (1 << 18)
+#define SUS_PWR_FLR (1 << 16)
+#define PWR_FLR (1 << 14)
#define RPS (1 << 2)
#define SLEEP_AFTER_POWER_FAIL (1 << 0)
#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \
- WARM_RESET_STS | GLOBAL_RESET_STS | \
+ WARM_RESET_STS | GBL_RST_STS | \
SRS | MS4V)
#define GEN_PMCON2 0x1024
+#define GEN_PMCON_B GEN_PMCON2
#define LPC_LPB_CLK_CTRL ((1 << 11) | (1 << 12) | (1 << 13))
#define BIOS_PCI_EXP_EN (1 << 10)
#define PWRBTN_LVL (1 << 9)