diff options
| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-04-01 19:01:59 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-07 16:19:56 +0000 |
| commit | 4b45d4c8028026fca45f16f37896b0f24434a3d1 (patch) | |
| tree | 26866187ded80f6037f898897f1ffcaf30ff47b9 /src/soc/intel | |
| parent | 369b9ad78705fcc2bfa0ad6672e61c2d3cc135f8 (diff) | |
soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
The FSP needs to program VrPowerDeliverDesign configuration per
platform according to the platform capabilities to avoid incorrect
electrial/power parameters. This value is an enum of the available
power delivery segments that are defined in the Platform Design
Guide.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I74859e6735e59a15084a9e690b43f68341862833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 2 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a69e6455ee..2dae9cd202 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -441,6 +441,13 @@ struct soc_intel_alderlake_config { uint8_t dmi_power_optimize_disable; /* + * Used to communicate the power delivery design capability of the board. This + * value is an enum of the available power delivery segments that are defined in + * the Platform Design Guide. + */ + uint8_t vr_power_delivery_design; + + /* * Enable(1)/Disable(0) CPU Replacement check. * Default 0. Setting this to 1 to check CPU replacement. */ diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index bd2c0bea0e..bd41480e75 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -748,6 +748,8 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, } s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion; + + s_cfg->VrPowerDeliveryDesign = config->vr_power_delivery_design; } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |