diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-09-23 15:06:37 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-09-26 23:52:32 +0200 |
| commit | c64a6d63ed9cbd20d8acd8d50ce76af275cca526 (patch) | |
| tree | 0fffc54b320c9bd57410560f2bcbd54bf791ee42 /src/soc/intel | |
| parent | fe222005b813975d7370fd8c91a10fc46e4f9c93 (diff) | |
soc/intel/apollolake: provide power button ACPI device
Instead of having each mainboard provide the power button,
uncondtionally provide the power button ACPI device on behalf
of each mainboard.
BUG=chrome-os-partner:56677
Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16731
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/southbridge.asl | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index d7ced0f924..1c10f1a5ed 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,6 +17,15 @@ #include <soc/gpe.h> +/* Power button. */ +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} + /* PCIE device */ #include "pcie.asl" |