soc/intel/xeon_sp: Add Granite Rapids initial codes

coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.

This patch initially sets the code set up as a build target with
Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids).

1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmitsburg PCH)'s codes are reused.

2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.

Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

1 files changed, 34 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/gnr/acpi/gpe.asl b/src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
new file mode 100644
index 0000000000..b61ffcf4fb
--- /dev/null
+++ b/src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/iomap.h>
+
+Scope (\_SB)
+{
+	Scope (\_GPE)
+	{
+		OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0xFF)
+		Field (PMIO, ByteAcc, NoLock, Preserve) {
+			Offset(0x34),   /* 0x34, SMI/SCI STS*/
+				,  9,
+			SGCS, 1,        /* SWGPE STS BIT */
+
+			Offset(0x40),   /* 0x40, SMI/SCI_EN*/
+				,  17,
+			SGPC, 1,        /* SWGPE CTRL BIT */
+
+			Offset(0x6C),   /* 0x6C, General Purpose Event 0 Status [127:96] */
+				,  2,
+			SGPS,  1,       /* SWGPE STATUS */
+
+			Offset(0x7C),   /* 0x7C, General Purpose Event 0 Enable [127:96] */
+				,  2,
+			SGPE,  1        /* SWGPE ENABLE */
+		}
+		Method (_L62, 0, NotSerialized)
+		{
+			DBGO("\\_GPE\\_L62\n")
+			SGPC = 0 // clear SWGPE control
+			SGPS = 1 // clear SWGPE Status
+		}
+	}
+}