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| author | Lu, Pen-ChunX <pen-chunx.lu@intel.com> | 2024-05-07 22:42:12 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-01 15:32:25 +0000 |
| commit | 00d538b562f2be74a9b65df3cc68b0ec68417a7f (patch) | |
| tree | 0bf651520f8b7fa05a73f5ec2692db219e0c5107 /src/soc/intel/xeon_sp/chip_gen1.c | |
| parent | 188909aad4ba3eeadba2c7ad6fc08858800b8f7d (diff) | |
soc/intel/xeon_sp: Add acpigen_write_pci_root_port
acpigen_write_pci_root_port writes SSDT device objects for PCIe
root port, _ADR and _BBN are provided. SSDT objects for direct
subordinate devices will also be created (if detected), _ADR and
_SUN are provided.
TEST=Build and boot on intel/archercity CRB
Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0
Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/chip_gen1.c')
0 files changed, 0 insertions, 0 deletions