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authorElyes Haouas <ehaouas@noos.fr>2022-10-11 13:56:30 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-10-12 14:18:35 +0000
commit987f1f439b3fb73a68966ba83e0ae0f669cd4052 (patch)
tree0aa704c208abd1bf6b42e7e4f3251ca4e1e46e47 /src/soc/intel/tigerlake
parent85f87e823f6c27bb9ad7811cf669173806237e0c (diff)
treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/acpi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index 6e13aba780..573dc5ff55 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -156,7 +156,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
+ fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
fadt->x_pm_tmr_blk.addrh = 0x0;
if (config->s0ix_enable)