diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-11-18 15:07:33 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-26 23:39:16 +0000 |
| commit | 9018dee6856791ab599463a771826936c20a80bb (patch) | |
| tree | 079e966e6b894bb9c81ca25e9e783c28947e0e64 /src/soc/intel/tigerlake | |
| parent | 5aa98964fb4e2e8c10b1663f8d6a3faa2b700410 (diff) | |
src/soc/intel: Remove unnecessary space after casts
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/bootblock/pch.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/pmutil.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 9758dba253..fc06873259 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -56,7 +56,7 @@ static void soc_config_pwrmbase(void) pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); + setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index d7c60bee66..13c5fc0996 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -319,7 +319,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); /* D3Hot and D3Cold for TCSS */ params->D3HotEnable = !config->TcssD3HotDisable; diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 9aca5c2b2c..b8bf975bde 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -268,7 +268,7 @@ void soc_fill_power_state(struct chipset_power_state *ps) /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } /* |