diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-05-21 10:41:32 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-22 18:10:40 +0000 |
| commit | 34e3fac130d7c5c45d4fd583f41bf7b632697681 (patch) | |
| tree | c5b2293c0ce534da0254de63eef124632e1b7f4d /src/soc/intel/tigerlake | |
| parent | 121ff627689834c4d0517ae151eb355ad548d285 (diff) | |
soc/intel/tigerlake: Replace spaces with tabs
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9b64375d905d93a8db726202ed2ce932fa536da3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 6b26231c1b..2d40dc31e4 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -6,19 +6,19 @@ * port of the USB4/TBT topology. */ /* Number of microseconds to wait after a conventional reset */ -#define FW_RESET_TIME 50000 +#define FW_RESET_TIME 50000 /* Number of microseconds to wait after data link layer active report */ -#define FW_DL_UP_TIME 1 +#define FW_DL_UP_TIME 1 /* Number of microseconds to wait after a function level reset */ -#define FW_FLR_RESET_TIME 1 +#define FW_FLR_RESET_TIME 1 /* Number of microseconds to wait from D3 hot to D0 transition */ -#define FW_D3HOT_TO_D0_TIME 50000 +#define FW_D3HOT_TO_D0_TIME 50000 /* Number of microseconds to wait after setting the VF enable bit */ -#define FW_VF_ENABLE_TIME 1 +#define FW_VF_ENABLE_TIME 1 OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) Field (PXCS, AnyAcc, NoLock, Preserve) |