diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2023-04-07 17:05:49 +0000 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2023-04-12 15:19:56 +0000 |
| commit | 076f86125f5578b0cc58fa219f80a5a39af31b99 (patch) | |
| tree | e3c45d9f751a693f1e7e5a4e24d75dc84230fcfa /src/soc/intel/tigerlake | |
| parent | 7c722ce1795e58b3b5b3feb3053b850587e748d1 (diff) | |
Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"
This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282.
Reason for revert: dependency for revert CB:73903
Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index a10db87202..b823f50301 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -323,12 +323,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* D3Hot and D3Cold for TCSS */ params->D3HotEnable = !config->TcssD3HotDisable; - cpu_id = cpu_get_cpuid(); if (cpu_id == CPUID_TIGERLAKE_A0) params->D3ColdEnable = 0; else - params->D3ColdEnable = CONFIG(D3COLD_SUPPORT); + params->D3ColdEnable = !config->TcssD3ColdDisable; params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; |