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authorSubrata Banik <subrata.banik@intel.com>2020-10-04 14:16:31 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-10-05 15:17:53 +0000
commit37a42da4658f4c9fb4645ffab48c9eec4e831573 (patch)
treebce728eb3b0470749480f81f5fafa6e8b95d31fe /src/soc/intel/tigerlake
parentb70c66b00d5741d3ba4eac96d75defab0dbec434 (diff)
soc/intel/common/block/acpi: Factor out common ish.asl
This patch moves ish.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CML platform. 1) Dump and disassemble DSDT, verify ISHB device present inside common ish.asl is still there with correct _ADR value. 2) Verify no ACPI error seen while running 'dmesg` from console. CML platform: Device (ISHB) { Name (_ADR, 0x00130000) // _ADR: Address Name (_DDN, "Integrated Sensor Hub Controller") //_DDN: DOS Device Name } TGL/JSL platform: Device (ISHB) { Name (_ADR, 0x00120000) // _ADR: Address Name (_DDN, "Integrated Sensor Hub Controller") //_DDN: DOS Device Name } Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I33c1649d7a632c7b147e1bf307cfb5c1dfd84c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/45995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/acpi/ish.asl9
-rw-r--r--src/soc/intel/tigerlake/acpi/southbridge.asl2
2 files changed, 1 insertions, 10 deletions
diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl
deleted file mode 100644
index 5c8b130315..0000000000
--- a/src/soc/intel/tigerlake/acpi/ish.asl
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Intel Integrated Sensor Hub Controller 0:12.0 */
-
-Device (ISHB)
-{
- Name (_ADR, 0x00120000)
- Name (_DDN, "Integrated Sensor Hub Controller")
-}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 7d6a0fbad0..373dca5840 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -33,7 +33,7 @@
#include <soc/intel/common/block/acpi/acpi/smbus.asl>
/* ISH 0:12.0 */
-#include "ish.asl"
+#include <soc/intel/common/block/acpi/acpi/ish.asl>
/* USB XHCI 0:14.0 */
#include "xhci.asl"