diff options
author | Elyes Haouas <ehaouas@noos.fr> | 2024-03-23 15:40:00 +0100 |
---|---|---|
committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-03-30 08:29:38 +0000 |
commit | c0d3cf105254c0bbde5c57c8817f5263271fb0fe (patch) | |
tree | b76d060dcb00f6696ded9e39bdc7a7808bcb1e72 /src/soc/intel/tigerlake | |
parent | 57351dd872746392175f5684b04ac9fb0a5d5538 (diff) |
soc/intel: Remove blank lines before '}' and after '{'
Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r-- | src/soc/intel/tigerlake/chip.h | 1 | ||||
-rw-r--r-- | src/soc/intel/tigerlake/crashlog_lib.c | 1 | ||||
-rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 1 | ||||
-rw-r--r-- | src/soc/intel/tigerlake/meminit.c | 1 | ||||
-rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 1 | ||||
-rw-r--r-- | src/soc/intel/tigerlake/romstage/romstage.c | 1 |
6 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 8700dd5d51..f8d4d4907b 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -116,7 +116,6 @@ enum ddi_port_config { }; struct soc_intel_tigerlake_config { - /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; diff --git a/src/soc/intel/tigerlake/crashlog_lib.c b/src/soc/intel/tigerlake/crashlog_lib.c index bde641d475..fca38a1c35 100644 --- a/src/soc/intel/tigerlake/crashlog_lib.c +++ b/src/soc/intel/tigerlake/crashlog_lib.c @@ -116,7 +116,6 @@ u32 cl_get_cpu_tmp_bar(void) bool cl_pmc_sram_has_mmio_access(void) { - if (pci_read_config16(PCH_DEV_SRAM, PCI_VENDOR_ID) == 0xFFFF) { printk(BIOS_ERR, "PMC SSRAM PCI device is disabled.\n"); return false; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 33269356c8..d5472dd91b 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -563,7 +563,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchFivrExtV1p05RailIccMaximum = config->ext_fivr_settings.v1p05_icc_max_ma; - } /* Apply minimum assertion width settings if non-zero */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index d4f96689f0..df9ba2dce3 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -176,5 +176,4 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, default: die("Unsupported memory type(%d)\n", mb_cfg->type); } - } diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index baf2eb36cf..f7337f024d 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -221,7 +221,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, config->ibecc.region_mask); } } - } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 31b19d2265..1985ea3c5b 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -150,5 +150,4 @@ void mainboard_romstage_entry(void) save_dimm_info(); } - } |