diff options
| author | CoolStar <coolstarorganization@gmail.com> | 2024-02-23 12:09:22 -0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2024-02-27 20:41:22 +0000 |
| commit | 377845a9d4f306082b8fcce3802f0d5e880647f3 (patch) | |
| tree | 3b4c49c1fd14253b38d71d4f2b93f194d94f2afa /src/soc/intel/tigerlake | |
| parent | 9bbfafbef89aef741e123349d5f2e1100eefd154 (diff) | |
soc/intel/tigerlake: Fix processor hang while plug unplug of TBT device
Port 9c348a7b7ea3 ("soc/intel/alderlake: Fix processor hang while plug
unplug of TBT device") from Alder Lake to fix a similar issue present
on Tiger Lake:
> Processor hang is observed while hot plug unplug of TBT device. BIOS
> should execute TBT PCIe RP RTD3 flow based on the value of
> TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if
> BIT30 in TBT FW version is not set.
> BUG=b:194880254
> https://review.coreboot.org/c/coreboot/+/56503
Change-Id: Ie5409111d4239be86c0b153f01b4fe5fc6af352c
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80718
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss.asl | 8 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss_dma.asl | 3 |
2 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 5af78edb8a..608b46450d 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -567,6 +567,10 @@ Scope (\_SB.PCI0) /* DMA0 is not in D3Cold now. */ \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ + If (\_SB.PCI0.TDM0.IF30 != 1) { + Return + } + Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { /* Put RP0 to D3 cold. */ @@ -622,6 +626,10 @@ Scope (\_SB.PCI0) /* DMA1 is not in D3Cold now */ \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ + If (\_SB.PCI0.TDM0.IF30 != 1) { + Return + } + Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { /* Put RP2 to D3 cold. */ diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index 90824698bb..2586ecbbc7 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -11,7 +11,8 @@ Field (DPME, AnyAcc, NoLock, Preserve) , 6, PMES, 1, /* 15, PME_STATUS */ Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ - , 31, + , 30, + IF30, 1, /* ITBT FW Version Bit30 */ INFR, 1, /* TBT NVM FW Ready */ Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ TB2P, 32, /* TBT to PCIe */ |