diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2020-01-17 18:56:58 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-02-27 12:03:42 +0000 |
| commit | dba6c4cfc08db8cb41b3f40d9ac9e03f92056046 (patch) | |
| tree | 9240c1f9138084d5d49efe3e88764f1d485a738c /src/soc/intel/tigerlake/spi.c | |
| parent | de36d7ebfa52f4cfa2ca9b1f477a2deee6a487f4 (diff) | |
soc/intel/tigerlake: Update FSP params for Jasper Lake
Update FSP parameters for various configurations like:
- graphics
- USB
- PCIe root ports
- SD card
- eMMC
- Audio
- Basic UART configuration
These are the initial settings for JSL.
This patch also corrects the debug_interface_flag definitions.
TEST=Build dedede board
Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/spi.c')
0 files changed, 0 insertions, 0 deletions