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| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 13:23:18 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:12:44 +0000 |
| commit | bbc80f4405a1ba12ad444ef900da6a55d63f45b8 (patch) | |
| tree | 85249be08e8da68f9f7d1aaa5d09454f00febb83 /src/soc/intel/tigerlake/spd/ddr4-spd-4.hex | |
| parent | 1318ab475ddcae5fdd8f41b66c4d7034c8b3d396 (diff) | |
nb/intel/x4x: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Moreover, the ASL reservation for MMCONFIG was only for 64 busses.
Change-Id: I7366a5096aacd92401535be020358447650b4247
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/spd/ddr4-spd-4.hex')
0 files changed, 0 insertions, 0 deletions