soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

This change adds support for Intel Atom Processors P5300, P5700
product families (known as Snow Ridge NS and Snow Ridge NX).

Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Tested-by: Vasiliy Khoruzhick <vasilykh@arista.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>

1 files changed, 33 insertions, 0 deletions

diff --git a/src/soc/intel/snowridge/lockdown.c b/src/soc/intel/snowridge/lockdown.c
new file mode 100644
index 0000000000..b74b74ca4b
--- /dev/null
+++ b/src/soc/intel/snowridge/lockdown.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_ops.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/pmclib.h>
+#include <intelpch/lockdown.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/pmc.h>
+
+#define SMM_FEATURE_CONTROL      0x8c
+#define SMM_CODE_CHK_EN          (1 << 2)
+#define SMM_FEATURE_CONTROL_LOCK (1 << 0)
+
+static void pmc_lockdown_cfg(int chipset_lockdown)
+{
+	pmc_or_mmio32(PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
+	pmc_or_mmio32(GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
+
+	pmc_global_reset_disable_and_lock();
+
+	assert(chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT);
+
+	pmc_or_mmio32(GEN_PMCON_B, SMI_LOCK);
+}
+
+void soc_lockdown_config(int chipset_lockdown)
+{
+	pmc_lockdown_cfg(chipset_lockdown);
+
+	pci_or_config32(UBOX_DEV_RACU, SMM_FEATURE_CONTROL,
+			SMM_CODE_CHK_EN | SMM_FEATURE_CONTROL_LOCK);
+}