soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

This change adds support for Intel Atom Processors P5300, P5700
product families (known as Snow Ridge NS and Snow Ridge NX).

Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Tested-by: Vasiliy Khoruzhick <vasilykh@arista.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>

1 files changed, 36 insertions, 0 deletions

diff --git a/src/soc/intel/snowridge/heci.c b/src/soc/intel/snowridge/heci.c
new file mode 100644
index 0000000000..3bc9d5f21f
--- /dev/null
+++ b/src/soc/intel/snowridge/heci.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <device/resource.h>
+
+static void heci_read_resources(struct device *dev)
+{
+	struct resource *res = NULL;
+
+	pci_dev_read_resources(dev);
+
+	/**
+	 * Clear `IORESOURCE_PCI64` since we want this device to remain under 4G as it is used
+	 * by FSP Notify.
+	 */
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res->limit = 0xffffffff;
+	res->flags &= ~IORESOURCE_PCI64;
+}
+
+static struct device_operations snr_heci_ops = {
+	.read_resources = heci_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.ops_pci = &pci_dev_ops_pci,
+};
+
+static const struct pci_driver snr_heci_driver __pci_driver = {
+	.ops = &snr_heci_ops,
+	.vendor = PCI_VID_INTEL,
+	.device = PCI_DID_INTEL_SNR_HECI1,
+};