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| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-06-25 11:23:03 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-17 13:47:25 +0000 |
| commit | 8d4e67da2046a5a6f55cd803c77b32d0c621cbc5 (patch) | |
| tree | f16121b417c6f9f4800df1ec0d90831342d9ff1d /src/soc/intel/skylake | |
| parent | c78521b3761d9afd44db630b0ebe7b96acc44bd3 (diff) | |
soc/intel/elkhartlake: Expose FIVR config to mainboard
Elkhart Lake provides option to configure FIVR (Fully Integrated
Voltage Regulators) via parameters in FSP-S.
This CL removes fixed FIVR config values and expose these parameters
to the devicetree so that they can be configured on mainboard level
as needed.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/skylake')
0 files changed, 0 insertions, 0 deletions