diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-10 10:26:52 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-01-26 08:30:01 +0000 |
| commit | af2f8b92974cc698f72fc1e2a1979293611c029f (patch) | |
| tree | f70a092c6217696d33289c8151d619d0497e486b /src/soc/intel/skylake/pmc.c | |
| parent | 393b093f715cb4ccf71922ac2ed4bd73a18bcacc (diff) | |
soc/intel/alderlake: Choose non-posted write to lock GPIO PAD
Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI config on Alder Lake
to instruct Pad Configuration Lock to use non-posted sideband writes as
posted write is not supported on Alder Lake while locking GPIO pads.
BUG=b:211573253, b:211950520
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id8d394b97de9c328b3f75df3649d7efc782f006b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/skylake/pmc.c')
0 files changed, 0 insertions, 0 deletions