soc/intel/skylake: drop support for FSP 1.1

This drops support for FSP 1.1 in soc/intel/skylake, after all boards
have been migrated to FSP 2.0, which is backwards compatible.

Any moving of files happens in a follow-up commit to make review easier.

Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 0 insertions, 64 deletions

diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
deleted file mode 100644
index 2071d58b49..0000000000
--- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_RAMSTAGE_H_
-#define _SOC_RAMSTAGE_H_
-
-#include <device/device.h>
-#include <fsp/ramstage.h>
-#include <fsp/soc_binding.h>
-
-#include "../../../chip.h"
-
-#define FSP_SIL_UPD SILICON_INIT_UPD
-#define FSP_MEM_UPD MEMORY_INIT_UPD
-
-void soc_irq_settings(FSP_SIL_UPD *params);
-void soc_init_pre_device(void *chip_info);
-void soc_fsp_load(void);
-const char *soc_acpi_name(const struct device *dev);
-
-/* Get igd framebuffer bar */
-uintptr_t fsp_soc_get_igd_bar(void);
-
-#endif
diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
deleted file mode 100644
index 386931043d..0000000000
--- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_ROMSTAGE_H_
-#define _SOC_ROMSTAGE_H_
-
-#include <fsp/romstage.h>
-
-void systemagent_early_init(void);
-void intel_early_me_status(void);
-void enable_smbus(void);
-int smbus_read_byte(unsigned int device, unsigned int address);
-
-#endif /* _SOC_ROMSTAGE_H_ */