soc/intel/common/gpio: Perform GPIO PAD lock outside SMM

This patch performs GPIO PAD lock configuration in non-smm mode.
Typically, coreboot enables SMI at latest boot phase post FSP-S,
hence, FSP-S might get chance to perform GPP lock configuration.

With this code changes, coreboot is able to perform GPIO PAD
lock configuration early in the boot flow, prior to calling FSP-S.

Also, this patch ensures to have two possible options as per GPIO
BWG to lock the GPIO PAD configuration.
1. Using SBI message with opcode 0x13
2. Using Private Configuration Register (PCR)

BUG=b:211573253, b:211950520
TEST=Able to build and boot brya variant with this code change.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I71b4e2f24303b6acb56debd581bd6bc818b6f926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60801
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions