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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-03-29 15:34:07 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-04-02 06:27:50 +0000 |
| commit | f7f7b3bbf6827494985afae5f10312e63d6a8049 (patch) | |
| tree | f6f3bc60c9e05956cad4b6708b248a52fef83324 /src/soc/intel/quark/reset.c | |
| parent | 3453c313acf7d1a6d26ef649b47dc1c3c0c7b677 (diff) | |
soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
Add the 28W TDP version of the ADL-P with MCHID 0x4629.
Verified that all 28W SoCs have the same PL1/PL2 defined
in Intel document #655258 "12th Generation Intel Core
Processors Datasheet, Volume 1 of 2".
Fixes the error seen in coreboot log:
[ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration
Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Diffstat (limited to 'src/soc/intel/quark/reset.c')
0 files changed, 0 insertions, 0 deletions