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authorRob Barnes <robbarnes@google.com>2021-11-02 17:47:47 -0600
committerKarthik Ramasubramanian <kramasub@google.com>2021-11-22 16:30:08 +0000
commitb35acf9210ffdd458a806ddbbf7deef7aac20fcd (patch)
treeae50e227433bc5563e231339a99c1d692c619c8b /src/soc/intel/quark/chip.h
parent2c89d08d7eff7007b4ef48aa333085d20cd74bb9 (diff)
soc/amd/psp_verstage: Init TPM on S0i3 resume
Add option to initialize the TPM in PSP verstage during s0i3 resume. This is needed if the TPM is reset in s0i3. FSDL is handling restoring everything else, so only the minimum TPM initialization is done. Move aoac and i2c init before psp_verstrage_s0i3_resume becasue i2c needs to be ready before attempting to restore tpm. BUG=b:200578885,b:197965075 TEST=Multiple cycles of S0i3 suspend resume. ~66ms of additional delay. BRANCH=None Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/quark/chip.h')
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