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authorSubrata Banik <subratabanik@google.com>2023-09-22 12:54:43 +0530
committerSubrata Banik <subratabanik@google.com>2023-09-23 09:26:05 +0000
commit0cd873f585f92de81476849f2aa1c6e1a47b26c3 (patch)
treeaaed17da278d1fa1a0126bdf7a8181d05c8e45cf /src/soc/intel/meteorlake
parent9c58830a23efff2f90279d05a839e0892d849e1b (diff)
soc/intel/meteorlake: Reduce memory test size
Enable upd to reduce size of the memory test. BUG=b:301441204 TEST=Able to build and boot google/rex. w/o this patch: 951:returning from FspMemoryInit 650,922 (79,560) w/ this patch: 951:returning from FspMemoryInit 618,490 (45,621) Change-Id: I903591ec749d270a98895dafb2d8f8d0b287c26a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78067 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc/intel/meteorlake')
-rw-r--r--src/soc/intel/meteorlake/chipset.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 59eb2c96d6..ce4fe08850 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -14,6 +14,9 @@ chip soc/intel/meteorlake
.tdp_pl4 = 120,
}"
+ # Reduce the size of BasicMemoryTests to speed up the boot time.
+ register "lower_basic_mem_test_size" = "true"
+
# NOTE: if any variant wants to override this value, use the same format
# as register "common_soc_config.pch_thermal_trip" = "value", instead of
# putting it under register "common_soc_config" in overridetree.cb file.