diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-05-30 14:18:32 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-06-06 17:52:32 +0000 |
| commit | 6876f49b7e3e8e750dc40ddbe1c37b6ab12c0153 (patch) | |
| tree | c21d4b5d95877ec0f93056eb76bf84f4aafa580a /src/soc/intel/meteorlake/bootblock/bootblock.c | |
| parent | ea4f8c28fdd4817b05eec3ef47088cf994ef7a26 (diff) | |
soc/intel/meteorlake: Refactor bootblock SoC programming code
This patch ensures the IP initialization being done as part of MTL
bootblock code is able to complete the bootblock phase without any
visible hang.
The re-ordering in the MTL bootblock SoC programming is required to
ensure the SA early initialization is taking place prior to
performing any PCI Read/Write operation (like P2SB bar enabling for
IOE die etc.).
Additionally, Fast SPI init takes place prior to enabling ROM caching
etc.
BUG=b:224325352
TEST= Able to build and start booting the MTL simics.
Without this change, the code execution is stuck as below:
[NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG] IGD: device id ffff (rev ff) is Unknown
[INFO ] PMC: Using default GPE route.
[INFO ] VBNV: CMOS invalid, restoring from flash
[ERROR] init_vbnv: failed to locate NVRAM
[EMERG] Cannot locate primary CBFS
Able to detect the Flash and reading the SPI flash layout in proper
with this change as below:
[NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG] IGD: device id ffff (rev ff) is Unknown
[INFO ] PMC: Using default GPE route.
[INFO ] VBNV: CMOS invalid, restoring from flash
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1804000.
[DEBUG] FMAP: base = 0x0 size = 0x2000000 #areas = 33
[DEBUG] FMAP: area RW_NVRAM found @ 112b000 (24576 bytes)
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/soc/intel/meteorlake/bootblock/bootblock.c')
| -rw-r--r-- | src/soc/intel/meteorlake/bootblock/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/meteorlake/bootblock/bootblock.c b/src/soc/intel/meteorlake/bootblock/bootblock.c index 74e9dca663..c7e1826d23 100644 --- a/src/soc/intel/meteorlake/bootblock/bootblock.c +++ b/src/soc/intel/meteorlake/bootblock/bootblock.c @@ -11,8 +11,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { - bootblock_ioe_die_early_init(); bootblock_soc_die_early_init(); + bootblock_ioe_die_early_init(); } void bootblock_soc_init(void) |